Go to the source code of this file.
Macros | |
#define | MACE_BASE 0x1f000000 |
#define | MACE_PCI_ERROR_ADDR 0x00 |
#define | MACE_PCI_ERROR_FLAGS 0x04 |
#define | MACE_PCI_CONTROL 0x08 |
#define | MACE_PCI_CONTROL_INT_MASK 0x000000ff |
#define | MACE_PCI_CONTROL_SERR_ENA 0x00000100 |
#define | MACE_PCI_CONTROL_ARB_N6 0x00000200 |
#define | MACE_PCI_CONTROL_PARITY_ERR 0x00000400 |
#define | MACE_PCI_CONTROL_MRMRA_ENA 0x00000800 |
#define | MACE_PCI_CONTROL_ARB_N3 0x00001000 |
#define | MACE_PCI_CONTROL_ARB_N4 0x00002000 |
#define | MACE_PCI_CONTROL_ARB_N5 0x00004000 |
#define | MACE_PCI_CONTROL_PARK_LIU 0x00008000 |
#define | MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000 |
#define | MACE_PCI_CONTROL_OVERRUN_INT 0x01000000 |
#define | MACE_PCI_CONTROL_PARITY_INT 0x02000000 |
#define | MACE_PCI_CONTROL_SERR_INT 0x04000000 |
#define | MACE_PCI_CONTROL_IT_INT 0x08000000 |
#define | MACE_PCI_CONTROL_RE_INT 0x10000000 |
#define | MACE_PCI_CONTROL_DPED_INT 0x20000000 |
#define | MACE_PCI_CONTROL_TAR_INT 0x40000000 |
#define | MACE_PCI_CONTROL_MAR_INT 0x80000000 |
#define | MACE_PCI_REV_INFO_R 0x0c |
#define | MACE_PCI_FLUSH_W 0x0c |
#define | MACE_PCI_CONFIG_ADDR 0xcf8 |
#define | MACE_PCI_CONFIG_DATA 0xcfc |
#define | MACE_PCI_LOW_MEMORY 0x1a000000 |
#define | MACE_PCI_LOW_IO 0x18000000 |
#define | MACE_PCI_NATIVE_VIEW 0x40000000 |
#define | MACE_PCI_IO 0x80000000 |
#define | MACE_PCI_HI_MEMORY 0x280000000 |
#define | MACE_PCI_HI_IO 0x100000000 |
#define | MACE_VIN1 0x100000 |
#define | MACE_VIN2 0x180000 |
#define | MACE_VOUT 0x200000 |
#define | MACE_PERIF 0x300000 |
#define | MACE_ISA_EXT 0x380000 |
#define | MACE_AUDIO 0 |
#define | MACE_ISA 0 |
#define | MACE_KBDMS 0 |
#define | MACE_I2C 0 |
#define | MACE_UST_MSC 0 |
#define | MACE_PERR_MASTER_ABORT 0x80000000 |
#define | MACE_PERR_TARGET_ABORT 0x40000000 |
#define | MACE_PERR_DATA_PARITY_ERR 0x20000000 |
#define | MACE_PERR_RETRY_ERR 0x10000000 |
#define | MACE_PERR_ILLEGAL_CMD 0x08000000 |
#define | MACE_PERR_SYSTEM_ERR 0x04000000 |
#define | MACE_PERR_INTERRUPT_TEST 0x02000000 |
#define | MACE_PERR_PARITY_ERR 0x01000000 |
#define | MACE_PERR_OVERRUN 0x00800000 |
#define | MACE_PERR_RSVD 0x00400000 |
#define | MACE_PERR_MEMORY_ADDR 0x00200000 |
#define | MACE_PERR_CONFIG_ADDR 0x00100000 |
#define | MACE_PERR_MASTER_ABORT_ADDR_VALID 0x00080000 |
#define | MACE_PERR_TARGET_ABORT_ADDR_VALID 0x00040000 |
#define | MACE_PERR_DATA_PARITY_ADDR_VALID 0x00020000 |
#define | MACE_PERR_RETRY_ADDR_VALID 0x00010000 |
#define | MACE_ISA_EPP_BASE (MACE_ISA_EXT + 0x00000) |
#define | MACE_ISA_ECP_BASE (MACE_ISA_EXT + 0x08000) |
#define | MACE_ISA_SER1_BASE (MACE_ISA_EXT + 0x10000) |
#define | MACE_ISA_SER2_BASE (MACE_ISA_EXT + 0x18000) |
#define | MACE_ISA_RTC_BASE (MACE_ISA_EXT + 0x20000) |
#define | MACE_ISA_GAME_BASE (MACE_ISA_EXT + 0x30000) |
#define | MACE_ISA_RINGBASE (MACE_ISA + 0x0000) |
#define | MACE_ISA_FLASH_NIC_REG (MACE_ISA + 0x0008) |
#define | MACE_ISA_FLASH_WE 0x01 /* 1=> Enable FLASH writes */ |
#define | MACE_ISA_PWD_CLEAR 0x02 /* 1=> PWD CLEAR jumper detected */ |
#define | MACE_ISA_NIC_DEASSERT 0x04 |
#define | MACE_ISA_NIC_DATA 0x08 |
#define | MACE_ISA_LED_RED 0x10 /* 1=> Illuminate RED LED */ |
#define | MACE_ISA_LED_GREEN 0x20 /* 1=> Illuminate GREEN LED */ |
#define | MACE_ISA_DP_RAM_ENABLE 0x40 |
#define | MACE_ISA_INT_STATUS (MACE_ISA + 0x0010) |
#define | MACE_ISA_INT_MASK (MACE_ISA + 0x0018) |
#define | MACE_ISA_INT_RTC_IRQ 0x00000100 |
#define | MACE_UST (MACE_UST_MSC + 0x00) /* Universial system time */ |
#define | MACE_COMPARE1 (MACE_UST_MSC + 0x08) /* Interrupt compare reg 1 */ |
#define | MACE_COMPARE2 (MACE_UST_MSC + 0x10) /* Interrupt compare reg 2 */ |
#define | MACE_COMPARE3 (MACE_UST_MSC + 0x18) /* Interrupt compare reg 3 */ |
#define | MACE_UST_PERIOD 960 /* UST Period in ns */ |
#define | MACE_AIN_MSC_UST (MACE_UST_MSC + 0x20) /* Audio in MSC/UST pair */ |
#define | MACE_AOUT1_MSC_UST (MACE_UST_MSC + 0x28) /* Audio out 1 MSC/UST pair */ |
#define | MACE_AOUT2_MSC_UST (MACE_UST_MSC + 0x30) /* Audio out 2 MSC/UST pair */ |
#define | MACE_VIN1_MSC_UST (MACE_UST_MSC + 0x38) /* Video In 1 MSC/UST pair */ |
#define | MACE_VIN2_MSC_UST (MACE_UST_MSC + 0x40) /* Video In 2 MSC/UST pair */ |
#define | MACE_VOUT_MSC_UST (MACE_UST_MSC + 0x48) /* Video out MSC/UST pair */ |
#define MACE_AIN_MSC_UST (MACE_UST_MSC + 0x20) /* Audio in MSC/UST pair */ |
Definition at line 172 of file sgi_macereg.h.
#define MACE_AOUT1_MSC_UST (MACE_UST_MSC + 0x28) /* Audio out 1 MSC/UST pair */ |
Definition at line 173 of file sgi_macereg.h.
#define MACE_AOUT2_MSC_UST (MACE_UST_MSC + 0x30) /* Audio out 2 MSC/UST pair */ |
Definition at line 174 of file sgi_macereg.h.
#define MACE_AUDIO 0 |
Definition at line 87 of file sgi_macereg.h.
#define MACE_BASE 0x1f000000 |
Definition at line 39 of file sgi_macereg.h.
#define MACE_COMPARE1 (MACE_UST_MSC + 0x08) /* Interrupt compare reg 1 */ |
Definition at line 167 of file sgi_macereg.h.
#define MACE_COMPARE2 (MACE_UST_MSC + 0x10) /* Interrupt compare reg 2 */ |
Definition at line 168 of file sgi_macereg.h.
#define MACE_COMPARE3 (MACE_UST_MSC + 0x18) /* Interrupt compare reg 3 */ |
Definition at line 169 of file sgi_macereg.h.
#define MACE_I2C 0 |
Definition at line 90 of file sgi_macereg.h.
#define MACE_ISA 0 |
Definition at line 88 of file sgi_macereg.h.
#define MACE_ISA_DP_RAM_ENABLE 0x40 |
Definition at line 150 of file sgi_macereg.h.
#define MACE_ISA_ECP_BASE (MACE_ISA_EXT + 0x08000) |
Definition at line 126 of file sgi_macereg.h.
#define MACE_ISA_EPP_BASE (MACE_ISA_EXT + 0x00000) |
Definition at line 125 of file sgi_macereg.h.
#define MACE_ISA_EXT 0x380000 |
Definition at line 83 of file sgi_macereg.h.
#define MACE_ISA_FLASH_NIC_REG (MACE_ISA + 0x0008) |
Definition at line 143 of file sgi_macereg.h.
#define MACE_ISA_FLASH_WE 0x01 /* 1=> Enable FLASH writes */ |
Definition at line 144 of file sgi_macereg.h.
#define MACE_ISA_GAME_BASE (MACE_ISA_EXT + 0x30000) |
Definition at line 130 of file sgi_macereg.h.
#define MACE_ISA_INT_MASK (MACE_ISA + 0x0018) |
Definition at line 155 of file sgi_macereg.h.
#define MACE_ISA_INT_RTC_IRQ 0x00000100 |
Definition at line 158 of file sgi_macereg.h.
#define MACE_ISA_INT_STATUS (MACE_ISA + 0x0010) |
Definition at line 154 of file sgi_macereg.h.
#define MACE_ISA_LED_GREEN 0x20 /* 1=> Illuminate GREEN LED */ |
Definition at line 149 of file sgi_macereg.h.
#define MACE_ISA_LED_RED 0x10 /* 1=> Illuminate RED LED */ |
Definition at line 148 of file sgi_macereg.h.
#define MACE_ISA_NIC_DATA 0x08 |
Definition at line 147 of file sgi_macereg.h.
#define MACE_ISA_NIC_DEASSERT 0x04 |
Definition at line 146 of file sgi_macereg.h.
#define MACE_ISA_PWD_CLEAR 0x02 /* 1=> PWD CLEAR jumper detected */ |
Definition at line 145 of file sgi_macereg.h.
#define MACE_ISA_RINGBASE (MACE_ISA + 0x0000) |
Definition at line 139 of file sgi_macereg.h.
#define MACE_ISA_RTC_BASE (MACE_ISA_EXT + 0x20000) |
Definition at line 129 of file sgi_macereg.h.
#define MACE_ISA_SER1_BASE (MACE_ISA_EXT + 0x10000) |
Definition at line 127 of file sgi_macereg.h.
#define MACE_ISA_SER2_BASE (MACE_ISA_EXT + 0x18000) |
Definition at line 128 of file sgi_macereg.h.
#define MACE_KBDMS 0 |
Definition at line 89 of file sgi_macereg.h.
#define MACE_PCI_CONFIG_ADDR 0xcf8 |
Definition at line 70 of file sgi_macereg.h.
#define MACE_PCI_CONFIG_DATA 0xcfc |
Definition at line 71 of file sgi_macereg.h.
#define MACE_PCI_CONTROL 0x08 |
Definition at line 46 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_ARB_N3 0x00001000 |
Definition at line 52 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_ARB_N4 0x00002000 |
Definition at line 53 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_ARB_N5 0x00004000 |
Definition at line 54 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_ARB_N6 0x00000200 |
Definition at line 49 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_DPED_INT 0x20000000 |
Definition at line 63 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_INT_MASK 0x000000ff |
Definition at line 47 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000 |
Definition at line 57 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_IT_INT 0x08000000 |
Definition at line 61 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_MAR_INT 0x80000000 |
Definition at line 65 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_MRMRA_ENA 0x00000800 |
Definition at line 51 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_OVERRUN_INT 0x01000000 |
Definition at line 58 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_PARITY_ERR 0x00000400 |
Definition at line 50 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_PARITY_INT 0x02000000 |
Definition at line 59 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_PARK_LIU 0x00008000 |
Definition at line 55 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_RE_INT 0x10000000 |
Definition at line 62 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_SERR_ENA 0x00000100 |
Definition at line 48 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_SERR_INT 0x04000000 |
Definition at line 60 of file sgi_macereg.h.
#define MACE_PCI_CONTROL_TAR_INT 0x40000000 |
Definition at line 64 of file sgi_macereg.h.
#define MACE_PCI_ERROR_ADDR 0x00 |
Definition at line 43 of file sgi_macereg.h.
#define MACE_PCI_ERROR_FLAGS 0x04 |
Definition at line 44 of file sgi_macereg.h.
#define MACE_PCI_FLUSH_W 0x0c |
Definition at line 69 of file sgi_macereg.h.
#define MACE_PCI_HI_IO 0x100000000 |
Definition at line 77 of file sgi_macereg.h.
#define MACE_PCI_HI_MEMORY 0x280000000 |
Definition at line 76 of file sgi_macereg.h.
#define MACE_PCI_IO 0x80000000 |
Definition at line 75 of file sgi_macereg.h.
#define MACE_PCI_LOW_IO 0x18000000 |
Definition at line 73 of file sgi_macereg.h.
#define MACE_PCI_LOW_MEMORY 0x1a000000 |
Definition at line 72 of file sgi_macereg.h.
#define MACE_PCI_NATIVE_VIEW 0x40000000 |
Definition at line 74 of file sgi_macereg.h.
#define MACE_PCI_REV_INFO_R 0x0c |
Definition at line 68 of file sgi_macereg.h.
#define MACE_PERIF 0x300000 |
Definition at line 82 of file sgi_macereg.h.
#define MACE_PERR_CONFIG_ADDR 0x00100000 |
Definition at line 115 of file sgi_macereg.h.
#define MACE_PERR_DATA_PARITY_ADDR_VALID 0x00020000 |
Definition at line 118 of file sgi_macereg.h.
#define MACE_PERR_DATA_PARITY_ERR 0x20000000 |
Definition at line 106 of file sgi_macereg.h.
#define MACE_PERR_ILLEGAL_CMD 0x08000000 |
Definition at line 108 of file sgi_macereg.h.
#define MACE_PERR_INTERRUPT_TEST 0x02000000 |
Definition at line 110 of file sgi_macereg.h.
#define MACE_PERR_MASTER_ABORT 0x80000000 |
Definition at line 104 of file sgi_macereg.h.
#define MACE_PERR_MASTER_ABORT_ADDR_VALID 0x00080000 |
Definition at line 116 of file sgi_macereg.h.
#define MACE_PERR_MEMORY_ADDR 0x00200000 |
Definition at line 114 of file sgi_macereg.h.
#define MACE_PERR_OVERRUN 0x00800000 |
Definition at line 112 of file sgi_macereg.h.
#define MACE_PERR_PARITY_ERR 0x01000000 |
Definition at line 111 of file sgi_macereg.h.
#define MACE_PERR_RETRY_ADDR_VALID 0x00010000 |
Definition at line 119 of file sgi_macereg.h.
#define MACE_PERR_RETRY_ERR 0x10000000 |
Definition at line 107 of file sgi_macereg.h.
#define MACE_PERR_RSVD 0x00400000 |
Definition at line 113 of file sgi_macereg.h.
#define MACE_PERR_SYSTEM_ERR 0x04000000 |
Definition at line 109 of file sgi_macereg.h.
#define MACE_PERR_TARGET_ABORT 0x40000000 |
Definition at line 105 of file sgi_macereg.h.
#define MACE_PERR_TARGET_ABORT_ADDR_VALID 0x00040000 |
Definition at line 117 of file sgi_macereg.h.
#define MACE_UST (MACE_UST_MSC + 0x00) /* Universial system time */ |
Definition at line 166 of file sgi_macereg.h.
#define MACE_UST_MSC 0 |
Definition at line 91 of file sgi_macereg.h.
#define MACE_UST_PERIOD 960 /* UST Period in ns */ |
Definition at line 170 of file sgi_macereg.h.
#define MACE_VIN1 0x100000 |
Definition at line 79 of file sgi_macereg.h.
#define MACE_VIN1_MSC_UST (MACE_UST_MSC + 0x38) /* Video In 1 MSC/UST pair */ |
Definition at line 175 of file sgi_macereg.h.
#define MACE_VIN2 0x180000 |
Definition at line 80 of file sgi_macereg.h.
#define MACE_VIN2_MSC_UST (MACE_UST_MSC + 0x40) /* Video In 2 MSC/UST pair */ |
Definition at line 176 of file sgi_macereg.h.
#define MACE_VOUT 0x200000 |
Definition at line 81 of file sgi_macereg.h.
#define MACE_VOUT_MSC_UST (MACE_UST_MSC + 0x48) /* Video out MSC/UST pair */ |
Definition at line 177 of file sgi_macereg.h.