mvme88k_vme.h Source File
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mvme88k_vme.h
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/* $OpenBSD: vme.h,v 1.17 2005/11/25 22:14:32 miod Exp $ */
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/*
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* Copyright (c) 1995 Theo de Raadt
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MVEME88K_DEV_VME_H__
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#define __MVEME88K_DEV_VME_H__
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#if 0
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struct
vmesoftc {
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struct
device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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struct
intrhand sc_abih;
/* `abort' switch */
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};
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#endif
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/*
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* XXX: this chip has some rather insane access rules!
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*/
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#define VME2_BASE 0xfff40000
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#define VME2_SADDR1 0x0000
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#define VME2_SADDR2 0x0004
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#define VME2_SLAVELMOD1 0x0008
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#define VME2_SLAVELMOD2 0x000c
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#define VME2_SLAVECTL 0x0010
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#define VME2_MASTER1 0x0014
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#define VME2_MASTER2 0x0018
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#define VME2_MASTER3 0x001c
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#define VME2_MASTER4 0x0020
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#define VME2_MASTER4MOD 0x0024
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#define VME2_MASTERCTL 0x0028
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#define VME2_GCSRCTL 0x002c
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#define VME2_DMACTL 0x0030
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#define VME2_DMAMODE 0x0034
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#define VME2_DMALADDR 0x0038
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#define VME2_DMAVMEADDR 0x003c
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#define VME2_DMACOUNT 0x0040
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#define VME2_DMATABLE 0x0044
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#define VME2_DMASTAT 0x0048
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#define VME2_TCR 0x004c
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#define VME2_T1CMP 0x0050
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#define VME2_T1COUNT 0x0054
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#define VME2_T2CMP 0x0058
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#define VME2_T2COUNT 0x005c
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#define VME2_TCTL 0x0060
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#define VME2_PRESCALE 0x0064
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#define VME2_IRQSTAT 0x0068
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#define VME2_IRQEN 0x006c
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#define VME2_SETSOFTIRQ 0x0070
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#define VME2_IRQCLR 0x0074
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#define VME2_IRQL1 0x0078
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#define VME2_IRQL2 0x007c
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#define VME2_IRQL3 0x0080
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#define VME2_IRQL4 0x0084
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#define VME2_VBR 0x0088
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#define VME2_MISC 0x008c
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#define VME2_SADDR_END 0xffff0000
/* VME address END & START */
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#define VME2_SADDR_START 0x0000ffff
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#define VME2_SADDR_LADDR 0xffff0000
/* local base address */
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#define VME2_SADDR_SIZE(mem) (0x1000 - (mem) >> 16)
/* encoding of size */
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#define VME2_SLAVE_CHOOSE(bits, num) ((bits) << (16*((num)-1)))
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#define VME2_SLAVECTL_WP 0x00000100
/* write posting */
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#define VME2_SLAVECTL_SNP_NO 0x00000000
/* no snooping */
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#define VME2_SLAVECTL_SNP_SINK 0x00000200
/* sink data */
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#define VME2_SLAVECTL_SNP_INVAL 0x00000400
/* invalidate */
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#define VME2_SLAVECTL_ADDER 0x00000800
/* use adder */
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#define VME2_SLAVECTL_SUP 0x00000080
/* modifier bit */
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#define VME2_SLAVECTL_USR 0x00000040
/* modifier bit */
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#define VME2_SLAVECTL_A32 0x00000020
/* modifier bit */
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#define VME2_SLAVECTL_A24 0x00000010
/* modifier bit */
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#define VME2_SLAVECTL_D64 0x00000008
/* modifier bit */
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#define VME2_SLAVECTL_BLK 0x00000004
/* modifier bit */
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#define VME2_SLAVECTL_PGM 0x00000002
/* modifier bit */
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#define VME2_SLAVECTL_DAT 0x00000001
/* modifier bit */
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#define VME2_MASTERCTL_4SHIFT 24
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#define VME2_MASTERCTL_3SHIFT 16
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#define VME2_MASTERCTL_2SHIFT 8
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#define VME2_MASTERCTL_1SHIFT 0
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#define VME2_MASTERCTL_D16 0x80
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#define VME2_MASTERCTL_WP 0x40
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#define VME2_MASTERCTL_AM 0x3f
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#define VME2_MASTERCTL_AM24SB 0x3f
/* A24 Supervisory Block Transfer */
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#define VME2_MASTERCTL_AM24SP 0x3e
/* A24 Supervisory Program Access */
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#define VME2_MASTERCTL_AM24SD 0x3d
/* A24 Supervisory Data Access */
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#define VME2_MASTERCTL_AM24UB 0x3b
/* A24 Non-priv. Block Transfer */
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#define VME2_MASTERCTL_AM24UP 0x3a
/* A24 Non-priv. Program Access */
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#define VME2_MASTERCTL_AM24UD 0x39
/* A24 Non-priv. Data Access */
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#define VME2_MASTERCTL_AM16S 0x2d
/* A16 Supervisory Access */
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#define VME2_MASTERCTL_AM16U 0x29
/* A16 Non-priv. Access */
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#define VME2_MASTERCTL_AM32SB 0x0f
/* A32 Supervisory Block Transfer */
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#define VME2_MASTERCTL_AM32SP 0x0e
/* A32 Supervisory Program Access */
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#define VME2_MASTERCTL_AM32SD 0x0d
/* A32 Supervisory Data Access */
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#define VME2_MASTERCTL_AM32UB 0x0b
/* A32 Non-priv. Block Transfer */
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#define VME2_MASTERCTL_AM32UP 0x0a
/* A32 Non-priv. Program Access */
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#define VME2_MASTERCTL_AM32UD 0x09
/* A32 Non-priv Data Access */
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#define VME2_MASTERCTL_ALL 0xff
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#define VME2_GCSRCTL_OFF 0xf0000000
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#define VME2_GCSRCTL_MDEN4 0x00080000
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#define VME2_GCSRCTL_MDEN3 0x00040000
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#define VME2_GCSRCTL_MDEN2 0x00020000
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#define VME2_GCSRCTL_MDEN1 0x00010000
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#define VME2_GCSRCTL_I2EN 0x00008000
/* F decode (A24D16/A32D16) on */
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#define VME2_GCSRCTL_I2WP 0x00004000
/* F decode write post */
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#define VME2_GCSRCTL_I2SU 0x00002000
/* F decode is supervisor */
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#define VME2_GCSRCTL_I2PD 0x00001000
/* F decode is program */
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#define VME2_GCSRCTL_I1EN 0x00000800
/* short decode (A16Dx) on */
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#define VME2_GCSRCTL_I1D16 0x00000400
/* short decode is D16 */
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#define VME2_GCSRCTL_I1WP 0x00000200
/* short decode write post */
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#define VME2_GCSRCTL_I1SU 0x00000100
/* short decode is supervisor */
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#define VME2_GCSRCTL_ROMSIZE 0x000000c0
/* size of ROM */
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#define VME2_GCSRCTL_ROMBSPD 0x00000038
/* speed of ROM */
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#define VME2_GCSRCTL_ROMASPD 0x00000007
/* speed of ROM */
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#define VME2_TCR_1MS (1 << 8)
/* Watchdog 1 ms */
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#define VME2_TCR_2MS (2 << 8)
/* Watchdog 2 ms */
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#define VME2_TCR_4MS (3 << 8)
/* Watchdog 4 ms */
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#define VME2_TCR_8MS (4 << 8)
/* Watchdog 8 ms */
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#define VME2_TCR_16MS (5 << 8)
/* Watchdog 16 ms */
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#define VME2_TCR_32MS (6 << 8)
/* Watchdog 32 ms */
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#define VME2_TCR_64MS (7 << 8)
/* Watchdog 64 ms */
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#define VME2_TCR_128MS (8 << 8)
/* Watchdog 128 ms */
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#define VME2_TCR_256MS (9 << 8)
/* Watchdog 256 ms */
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#define VME2_TCR_512MS (10 << 8)
/* Watchdog 512 ms */
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#define VME2_TCR_1S (11 << 8)
/* Watchdog 1 s */
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#define VME2_TCR_4S (12 << 8)
/* Watchdog 4 s */
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#define VME2_TCR_16S (13 << 8)
/* Watchdog 16 s */
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#define VME2_TCR_32S (14 << 8)
/* Watchdog 32 s */
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#define VME2_TCR_64S (15 << 8)
/* Watchdog 64 s */
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#define VME2_TCTL1_CEN 0x01
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#define VME2_TCTL1_COC 0x02
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#define VME2_TCTL1_COVF 0x04
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#define VME2_TCTL1_OVF 0xf0
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#define VME2_TCTL2_CEN (0x01 << 8)
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#define VME2_TCTL2_COC (0x02 << 8)
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#define VME2_TCTL2_COVF (0x04 << 8)
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#define VME2_TCTL2_OVF (0xf0 << 8)
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#define VME2_TCTL_WDEN 0x00010000
/* Watchdog Enable */
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#define VME2_TCTL_WDRSE 0x00020000
/* Watchdog Reset Enable */
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#define VME2_TCTL_WDSL 0x00040000
/* local or system reset */
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#define VME2_TCTL_WDBFE 0x00080000
/* Watchdog Board Fail Enable */
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#define VME2_TCTL_WDTO 0x00100000
/* Watchdog Timeout Status */
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#define VME2_TCTL_WDCC 0x00200000
/* Watchdog Clear Counter */
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#define VME2_TCTL_WDCS 0x00400000
/* Watchdog Clear Timeout */
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#define VME2_TCTL_SRST 0x00800000
/* system reset */
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#define VME2_TCTL_RSWE 0x01000000
/* Reset Switch Enable */
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#define VME2_TCTL_BDFLO 0x02000000
/* Assert Board Fail */
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#define VME2_TCTL_CPURS 0x04000000
/* Clear Power-up Reset bit */
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#define VME2_TCTL_PURS 0x08000000
/* Power-up Reset bit */
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#define VME2_TCTL_BDFLI 0x10000000
/* Board Fail Status*/
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#define VME2_TCTL_SYSFAIL 0x20000000
/* light SYSFAIL led */
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#define VME2_TCTL_SCON 0x40000000
/* we are SCON */
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#define VME2_IRQ_ACF 0x80000000
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#define VME2_IRQ_AB 0x40000000
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#define VME2_IRQ_SYSF 0x20000000
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#define VME2_IRQ_MWP 0x10000000
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#define VME2_IRQ_PE 0x08000000
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#define VME2_IRQ_V1IE 0x04000000
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#define VME2_IRQ_TIC2 0x02000000
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#define VME2_IRQ_TIC1 0x01000000
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#define VME2_IRQ_VIA 0x00800000
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#define VME2_IRQ_DMA 0x00400000
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#define VME2_IRQ_SIG3 0x00200000
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#define VME2_IRQ_SIG2 0x00100000
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#define VME2_IRQ_SIG1 0x00080000
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#define VME2_IRQ_SIG0 0x00040000
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#define VME2_IRQ_LM1 0x00020000
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#define VME2_IRQ_LM0 0x00010000
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#define VME2_IRQ_SW7 0x00008000
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#define VME2_IRQ_SW6 0x00004000
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#define VME2_IRQ_SW5 0x00002000
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#define VME2_IRQ_SW4 0x00001000
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#define VME2_IRQ_SW3 0x00000800
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#define VME2_IRQ_SW2 0x00000400
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#define VME2_IRQ_SW1 0x00000200
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#define VME2_IRQ_SW0 0x00000100
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#define VME2_IRQ_SW(x) ((1 << (x))) << 8)
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#define VME2_IRQ_SPARE 0x00000080
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#define VME2_IRQ_VME7 0x00000040
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#define VME2_IRQ_VME6 0x00000020
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#define VME2_IRQ_VME5 0x00000010
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#define VME2_IRQ_VME4 0x00000008
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#define VME2_IRQ_VME3 0x00000004
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#define VME2_IRQ_VME2 0x00000002
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#define VME2_IRQ_VME1 0x00000001
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#define VME2_IRQ_VME(x) (1 << ((x) - 1))
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#define VME2_IRQL1_ACFSHIFT 28
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#define VME2_IRQL1_ABSHIFT 24
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#define VME2_IRQL1_SYSFSHIFT 20
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#define VME2_IRQL1_WPESHIFT 16
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#define VME2_IRQL1_PESHIFT 12
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#define VME2_IRQL1_V1IESHIFT 8
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#define VME2_IRQL1_TIC2SHIFT 4
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#define VME2_IRQL1_TIC1SHIFT 0
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#define VME2_IRQL2_VIASHIFT 28
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#define VME2_IRQL2_DMASHIFT 24
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#define VME2_IRQL2_SIG3SHIFT 20
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#define VME2_IRQL2_SIG2SHIFT 16
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#define VME2_IRQL2_SIG1SHIFT 12
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#define VME2_IRQL2_SIG0SHIFT 8
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#define VME2_IRQL2_LM1SHIFT 4
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#define VME2_IRQL2_LM0SHIFT 0
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#define VME2_IRQL3_SW7SHIFT 28
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#define VME2_IRQL3_SW6SHIFT 24
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#define VME2_IRQL3_SW5SHIFT 20
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#define VME2_IRQL3_SW4SHIFT 16
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#define VME2_IRQL3_SW3SHIFT 12
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#define VME2_IRQL3_SW2SHIFT 8
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#define VME2_IRQL3_SW1SHIFT 4
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#define VME2_IRQL3_SW0SHIFT 0
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#define VME2_IRQL4_SPARESHIFT 28
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#define VME2_IRQL4_VME7SHIFT 24
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#define VME2_IRQL4_VME6SHIFT 20
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#define VME2_IRQL4_VME5SHIFT 16
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#define VME2_IRQL4_VME4SHIFT 12
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#define VME2_IRQL4_VME3SHIFT 8
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#define VME2_IRQL4_VME2SHIFT 4
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#define VME2_IRQL4_VME1SHIFT 0
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#define VME2_SYSFAIL (1 << 22)
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#define VME2_IOCTL1_MIEN (1 << 23)
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#define VME2_VBR_0SHIFT 28
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#define VME2_VBR_1SHIFT 24
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#define VME2_SET_VBR0(x) ((x) << VME2_VBR_0SHIFT)
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#define VME2_SET_VBR1(x) ((x) << VME2_VBR_1SHIFT)
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#define VME2_GET_VBR0(x) ((((x) >> 28) & 0xf) << 4)
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#define VME2_GET_VBR1(x) ((((x) >> 24) & 0xf) << 4)
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#define VME2_VBR_GPOXXXX 0x00ffffff
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#define VME2_MISC_MPIRQEN 0x00000080
/* do not set */
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#define VME2_MISC_REVEROM 0x00000040
/* 167: dis eprom. 166: en flash */
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#define VME2_MISC_DISSRAM 0x00000020
/* do not set */
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#define VME2_MISC_DISMST 0x00000010
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#define VME2_MISC_NOELBBSY 0x00000008
/* do not set */
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#define VME2_MISC_DISBSYT 0x00000004
/* do not set */
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#define VME2_MISC_ENINT 0x00000002
/* do not set */
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#define VME2_MISC_DISBGN 0x00000001
/* do not set */
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#define VME2_A16D32BASE 0xffff0000UL
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#define VME2_A16D32LEN 0x00010000UL
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#define VME2_A32D16BASE 0xf1000000UL
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#define VME2_A32D16LEN 0x01000000UL
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#define VME2_A16D16BASE 0xffff0000UL
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#define VME2_A16D16LEN 0x00010000UL
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#define VME2_A24D16BASE 0xf0000000UL
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#define VME2_A24D16LEN 0x01000000UL
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#define VME2_A16BASE 0xffff0000UL
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#define VME2_A24BASE 0xff000000UL
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#if 0
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paddr_t vmepmap(
struct
device *sc, off_t vmeaddr,
int
bustype);
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int
vmerw(
struct
device *sc,
struct
uio *uio,
int
flags,
int
bus);
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int
vmeintr_establish(
int
,
struct
intrhand *,
const
char
*);
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int
vme_findvec(
int
);
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int
vmescan(
struct
device *,
void
*,
void
*,
int
);
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#endif
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#endif
/* __MVEME88K_DEV_VME_H__ */
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