RISCV_CPUComponent.h Source File

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RISCV_CPUComponent.h
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1 #ifndef RISCV_CPUCOMPONENT_H
2 #define RISCV_CPUCOMPONENT_H
3 
4 /*
5  * Copyright (C) 2019 Anders Gavare. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  * derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  */
30 
31 // COMPONENT(riscv_cpu)
32 
33 #include <iomanip>
34 #include "CPUDyntransComponent.h"
35 
36 
37 // See https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf for
38 // calling convention.
39 
40 #define N_RISCV_XREGS 32
41 
42 static const char* RISCV_regnames[N_RISCV_XREGS] = {
43  "zero", // x0 = always zero
44  "ra", // x1 = return address Caller save
45  "sp", // x2 = stack pointer Callee save
46  "gp", // x3 = global pointer
47  "tp", // x4 = thread pointer
48  "t0", "t1", "t2", // x5..x7 = temporaries Caller save
49  "fp" /* or s0 */, // x8 = frame pointer Callee save
50  "s1", // x9 = saved register Callee save
51  "a0", "a1", // x10..x11 = arguments and return values Caller save
52  "a2", "a3", "a4", "a5", // x12..x17 = arguments Caller save
53  "a6", "a7",
54  "s2", "s3", "s4", "s5", // x18..x27 = saved registers Callee save
55  "s6", "s7", "s8", "s9",
56  "s10", "s11",
57  "t3", "t4", "t5", "t6", // x28..x31 = temporaries Caller save
58 };
59 
60 
61 // Each 16-bit part of an instruction is called a "parcel".
62 #define RISCV_MAX_PARCELS 12
63 
64 
65 #define RISCV_EXTENSION_C (1 << 1)
66 #define RISCV_EXTENSION_I (1 << 2)
67 
68 
69 /***********************************************************************/
70 
71 
72 /**
73  * \brief A Component representing a RISC-V processor.
74  */
76  : public CPUDyntransComponent
77 {
78 public:
79  /**
80  * \brief Constructs a RISCV_CPUComponent.
81  */
83 
84  /**
85  * \brief Creates a RISCV_CPUComponent.
86  */
88 
89  static string GetAttribute(const string& attributeName);
90 
91  virtual void ResetState();
92 
93  virtual bool PreRunCheckForComponent(GXemul* gxemul);
94 
95  virtual size_t DisassembleInstruction(uint64_t vaddr, vector<string>& result);
96 
97 
98  /********************************************************************/
99 
100  static void RunUnitTests(int& nSucceeded, int& nFailures);
101 
102 protected:
103  virtual bool CheckVariableWrite(StateVariable& var, const string& oldValue);
104 
105  virtual bool VirtualToPhysical(uint64_t vaddr, uint64_t& paddr, bool& writable);
106 
107  virtual string VirtualAddressAsString(uint64_t vaddr)
108  {
109  stringstream ss;
110  ss.flags(std::ios::hex | std::ios::right);
111  ss << std::setfill('0') << std::setw(16) << (uint64_t)vaddr;
112  return ss.str();
113  }
114 
115  virtual uint64_t PCtoInstructionAddress(uint64_t pc);
116 
117  virtual int FunctionTraceArgumentCount();
118  virtual int64_t FunctionTraceArgument(int n);
119  virtual bool FunctionTraceReturnImpl(int64_t& retval);
120 
121  virtual int GetDyntransICshift() const;
123 
124  virtual void ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const;
125 
126 private:
127  // TODO: Instructions.
128  // DECLARE_DYNTRANS_INSTR(b);
129  // DECLARE_DYNTRANS_INSTR(mov_lit_reg);
130 
131  void Translate(uint16_t iwords[], int nparcels, struct DyntransIC* ic);
132  DECLARE_DYNTRANS_INSTR(ToBeTranslated);
133 
134 private:
135  /*
136  * State:
137  */
138  string m_model;
139 
140  uint64_t m_extensions;
141 
142  uint64_t m_x[N_RISCV_XREGS];
143 };
144 
145 
146 #endif // RISCV_CPUCOMPONENT_H
RISCV_CPUComponent::VirtualAddressAsString
virtual string VirtualAddressAsString(uint64_t vaddr)
Format a virtual address as a displayable string.
Definition: RISCV_CPUComponent.h:107
N_RISCV_XREGS
#define N_RISCV_XREGS
Definition: RISCV_CPUComponent.h:40
RISCV_CPUComponent::RISCV_CPUComponent
RISCV_CPUComponent()
Constructs a RISCV_CPUComponent.
Definition: RISCV_CPUComponent.cc:38
RISCV_CPUComponent::GetDyntransToBeTranslated
virtual void(*)(CPUDyntransComponent *, DyntransIC *) GetDyntransToBeTranslated()
Definition: RISCV_CPUComponent.h:122
GXemul
The main emulator class.
Definition: GXemul.h:55
RISCV_CPUComponent::FunctionTraceReturnImpl
virtual bool FunctionTraceReturnImpl(int64_t &retval)
Definition: RISCV_CPUComponent.cc:144
StateVariable
StateVariables make up the persistent state of Component objects.
Definition: StateVariable.h:69
RISCV_CPUComponent::PreRunCheckForComponent
virtual bool PreRunCheckForComponent(GXemul *gxemul)
Checks the state of this component, before starting execution.
Definition: RISCV_CPUComponent.cc:87
RISCV_CPUComponent::FunctionTraceArgumentCount
virtual int FunctionTraceArgumentCount()
Definition: RISCV_CPUComponent.cc:132
refcount_ptr< Component >
CPUDyntransComponent
A base-class for processors Component implementations that use dynamic translation.
Definition: CPUDyntransComponent.h:91
RISCV_CPUComponent::GetDyntransICshift
virtual int GetDyntransICshift() const
Definition: RISCV_CPUComponent.cc:151
DyntransIC
Definition: CPUDyntransComponent.h:55
RISCV_CPUComponent::FunctionTraceArgument
virtual int64_t FunctionTraceArgument(int n)
Definition: RISCV_CPUComponent.cc:138
ic
struct arm_instr_call * ic
Definition: tmp_arm_multi.cc:50
RISCV_CPUComponent::RunUnitTests
static void RunUnitTests(int &nSucceeded, int &nFailures)
CPUDyntransComponent.h
RISCV_CPUComponent
A Component representing a RISC-V processor.
Definition: RISCV_CPUComponent.h:77
RISCV_CPUComponent::ShowRegisters
virtual void ShowRegisters(GXemul *gxemul, const vector< string > &arguments) const
Definition: RISCV_CPUComponent.cc:107
RISCV_CPUComponent::GetAttribute
static string GetAttribute(const string &attributeName)
Definition: RISCV_CPUComponent.cc:317
RISCV_CPUComponent::PCtoInstructionAddress
virtual uint64_t PCtoInstructionAddress(uint64_t pc)
Convert PC value to instuction address.
Definition: RISCV_CPUComponent.cc:174
RISCV_CPUComponent::ResetState
virtual void ResetState()
Resets the state variables of this component.
Definition: RISCV_CPUComponent.cc:74
RISCV_CPUComponent::CheckVariableWrite
virtual bool CheckVariableWrite(StateVariable &var, const string &oldValue)
Checks whether a write to a variable is OK.
Definition: RISCV_CPUComponent.cc:99
RISCV_CPUComponent::DisassembleInstruction
virtual size_t DisassembleInstruction(uint64_t vaddr, vector< string > &result)
Disassembles an instruction into readable strings.
Definition: RISCV_CPUComponent.cc:180
RISCV_CPUComponent::VirtualToPhysical
virtual bool VirtualToPhysical(uint64_t vaddr, uint64_t &paddr, bool &writable)
Virtual to physical address translation (MMU).
Definition: RISCV_CPUComponent.cc:165
ComponentCreateArgs
Definition: Component.h:49
RISCV_CPUComponent::Create
static refcount_ptr< Component > Create(const ComponentCreateArgs &args)
Creates a RISCV_CPUComponent.
Definition: RISCV_CPUComponent.cc:57

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