dp83932reg.h File Reference

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dp83932reg.h File Reference

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Classes

struct  sonic_rda16
 
struct  sonic_rda32
 
struct  sonic_rra16
 
struct  sonic_rra32
 
struct  sonic_frag16
 
struct  sonic_frag32
 
struct  sonic_tda16
 
struct  sonic_tda32
 
struct  sonic_cda16
 
struct  sonic_cda32
 

Macros

#define __attribute__(x)   /* */
 
#define __noreturn__   /* */
 
#define RDA_SEQNO_RBA(x)   (((x) >> 8) & 0xff)
 
#define RDA_SEQNO_RSN(x)   ((x) & 0xff)
 
#define RDA_LINK_EOL   0x01 /* end-of-list */
 
#define SONIC_NTXFRAGS   16
 
#define TDA_STATUS_NCOL(x)   (((x) >> 11) & 0x1f)
 
#define TDA_LINK_EOL   0x01 /* end-of-list */
 
#define SONIC_CR   0x00 /* Command Register */
 
#define CR_HTX   (1U << 0) /* Halt Transmission */
 
#define CR_TXP   (1U << 1) /* Transmit Packets */
 
#define CR_RXDIS   (1U << 2) /* Receiver Disable */
 
#define CR_RXEN   (1U << 3) /* Receiver Enable */
 
#define CR_STP   (1U << 4) /* Stop Timer */
 
#define CR_ST   (1U << 5) /* Start Timer */
 
#define CR_RST   (1U << 7) /* Software Reset */
 
#define CR_RRRA   (1U << 8) /* Read RRA */
 
#define CR_LCAM   (1U << 9) /* Load CAM */
 
#define SONIC_DCR   0x01 /* Data Configuration Register */
 
#define DCR_TFT0   (1U << 0) /* Transmit FIFO Threshold (lo) */
 
#define DCR_TFT1   (1U << 1) /* Transmit FIFO Threshold (hi) */
 
#define DCR_RFT0   (1U << 2) /* Receive FIFO Threshold (lo) */
 
#define DCR_RFT1   (1U << 3) /* Receive FIFO Threshold (hi) */
 
#define DCR_BMS   (1U << 4) /* Block Mode Select for DMA */
 
#define DCR_DW   (1U << 5) /* Data Width Select */
 
#define DCR_WC0   (1U << 6) /* Wait State Control (lo) */
 
#define DCR_WC1   (1U << 7) /* Wait State Control (hi) */
 
#define DCR_USR0   (1U << 8) /* User Definable Pin 0 */
 
#define DCR_USR1   (1U << 9) /* User Definable Pin 1 */
 
#define DCR_SBUS   (1U << 10) /* Synchronous Bus Mode */
 
#define DCR_PO0   (1U << 11) /* Programmable Output 0 */
 
#define DCR_PO1   (1U << 12) /* Programmable Output 1 */
 
#define DCR_LBR   (1U << 13) /* Latched Bus Retry */
 
#define DCR_EXBUS   (1U << 15) /* Extended Bus Mode */
 
#define SONIC_RCR   0x02 /* Receive Control Register */
 
#define RCR_PRX   (1U << 0) /* Packet Received OK */
 
#define RCR_LBK   (1U << 1) /* Loopback Packet Received */
 
#define RCR_FAER   (1U << 2) /* Frame Alignment Error */
 
#define RCR_CRCR   (1U << 3) /* CRC Error */
 
#define RCR_COL   (1U << 4) /* Collision Activity */
 
#define RCR_CRS   (1U << 5) /* Carrier Sense Activity */
 
#define RCR_LPKT   (1U << 6) /* Last Packet in RBA */
 
#define RCR_BC   (1U << 7) /* Broadcast Packet Received */
 
#define RCR_MC   (1U << 8) /* Multicast Packet Received */
 
#define RCR_LB0   (1U << 9) /* Loopback Control 0 */
 
#define RCR_LB1   (1U << 10) /* Loopback Control 1 */
 
#define RCR_AMC   (1U << 11) /* Accept All Multicast Packets */
 
#define RCR_PRO   (1U << 12) /* Physical Promiscuous Packets */
 
#define RCR_BRD   (1U << 13) /* Accept Broadcast Packets */
 
#define RCR_RNT   (1U << 14) /* Accept Runt Packets */
 
#define RCR_ERR   (1U << 15) /* Accept Packets with Errors */
 
#define SONIC_TCR   0x03 /* Transmit Control Register */
 
#define TCR_PTX   (1U << 0) /* Packet Transmitted OK */
 
#define TCR_BCM   (1U << 1) /* Byte Count Mismatch */
 
#define TCR_FU   (1U << 2) /* FIFO Underrun */
 
#define TCR_PMB   (1U << 3) /* Packet Monitored Bad */
 
#define TCR_OWC   (1U << 5) /* Out of Window Collision */
 
#define TCR_EXC   (1U << 6) /* Excessive Collisions */
 
#define TCR_CRSL   (1U << 7) /* Carrier Sense Lost */
 
#define TCR_NCRS   (1U << 8) /* No Carrier Sense */
 
#define TCR_DEF   (1U << 9) /* Deferred Transmission */
 
#define TCR_EXD   (1U << 10) /* Excessive Deferral */
 
#define TCR_EXDIS   (1U << 12) /* Disable Excessive Deferral Timer */
 
#define TCR_CRCI   (1U << 13) /* CRC Inhibit */
 
#define TCR_POWC   (1U << 14) /* Programmed Out of Window Col. Tmr */
 
#define TCR_PINT   (1U << 15) /* Programmable Interrupt */
 
#define SONIC_IMR   0x04 /* Interrupt Mask Register */
 
#define IMR_RFO   (1U << 0) /* Rx FIFO Overrun */
 
#define IMR_MP   (1U << 1) /* Missed Packet Tally */
 
#define IMR_FAE   (1U << 2) /* Frame Alignment Error Tally */
 
#define IMR_CRC   (1U << 3) /* CRC Tally */
 
#define IMR_RBA   (1U << 4) /* RBA Exceeded */
 
#define IMR_RBE   (1U << 5) /* Rx Buffers Exhausted */
 
#define IMR_RDE   (1U << 6) /* Rx Descriptors Exhausted */
 
#define IMR_TC   (1U << 7) /* Timer Complete */
 
#define IMR_TXER   (1U << 8) /* Transmit Error */
 
#define IMR_PTX   (1U << 9) /* Transmit OK */
 
#define IMR_PRX   (1U << 10) /* Packet Received */
 
#define IMR_PINT   (1U << 11) /* Programmable Interrupt */
 
#define IMR_LCD   (1U << 12) /* Load CAM Done */
 
#define IMR_HBL   (1U << 13) /* Heartbeat Lost */
 
#define IMR_BR   (1U << 14) /* Bus Retry Occurred */
 
#define SONIC_ISR   0x05 /* Interrupt Status Register */
 
#define SONIC_UTDAR   0x06 /* Upper Tx Descriptor Adress Register */
 
#define SONIC_CTDAR   0x07 /* Current Tx Descriptor Address Register */
 
#define SONIC_TPS   0x08 /* Transmit Packet Size */
 
#define SONIC_TFC   0x09 /* Transmit Fragment Count */
 
#define SONIC_TSA0   0x0a /* Transmit Start Address (lo) */
 
#define SONIC_TSA1   0x0b /* Transmit Start Address (hi) */
 
#define SONIC_TFS   0x0c /* Transmit Fragment Size */
 
#define SONIC_URDAR   0x0d /* Upper Rx Descriptor Address Register */
 
#define SONIC_CRDAR   0x0e /* Current Rx Descriptor Address Register */
 
#define SONIC_CRBA0   0x0f /* Current Receive Buffer Address (lo) */
 
#define SONIC_CRBA1   0x10 /* Current Receive Buffer Address (hi) */
 
#define SONIC_RBWC0   0x11 /* Remaining Buffer Word Count 0 */
 
#define SONIC_RBWC1   0x12 /* Remaining Buffer Word Count 1 */
 
#define SONIC_EOBC   0x13 /* End Of Buffer Word Count */
 
#define SONIC_URRAR   0x14 /* Upper Rx Resource Address Register */
 
#define SONIC_RSAR   0x15 /* Resource Start Address Register */
 
#define SONIC_REAR   0x16 /* Resource End Address Register */
 
#define SONIC_RRR   0x17 /* Resource Read Register */
 
#define SONIC_RWR   0x18 /* Resource Write Register */
 
#define SONIC_TRBA0   0x19 /* Temporary Receive Buffer Address (lo) */
 
#define SONIC_TRBA1   0x1a /* Temporary Receive Buffer Address (hi) */
 
#define SONIC_TBWC0   0x1b /* Temporary Buffer Word Count 0 */
 
#define SONIC_TBWC1   0x1c /* Temporary Buffer Word Count 1 */
 
#define SONIC_ADDR0   0x1d /* Address Generator 0 */
 
#define SONIC_ADDR1   0x1e /* Address Generator 1 */
 
#define SONIC_LLFA   0x1f /* Last Link Field Address */
 
#define SONIC_TTDA   0x20 /* Temporary Tx Descriptor Address */
 
#define SONIC_CEP   0x21 /* CAM Entry Pointer */
 
#define SONIC_CAP2   0x22 /* CAM Address Port 2 */
 
#define SONIC_CAP1   0x23 /* CAM Address Port 1 */
 
#define SONIC_CAP0   0x24 /* CAM Address Port 0 */
 
#define SONIC_CER   0x25 /* CAM Enable Register */
 
#define SONIC_CDP   0x26 /* CAM Descriptor Pointer */
 
#define SONIC_CDC   0x27 /* CAM Descriptor Count */
 
#define SONIC_SRR   0x28 /* Silicon Revision Register */
 
#define SONIC_WT0   0x29 /* Watchdog Timer 0 */
 
#define SONIC_WT1   0x2a /* Watchdog Timer 1 */
 
#define SONIC_RSC   0x2b /* Receive Sequence Counter */
 
#define SONIC_CRCETC   0x2c /* CRC Error Tally Count */
 
#define SONIC_FAET   0x2d /* Frame Alignment Error Tally */
 
#define SONIC_MPT   0x2e /* Missed Packet Tally */
 
#define SONIC_DCR2   0x3f /* Data Configuration Register 2 */
 
#define DCR2_RJCM   (1U << 0) /* Reject on CAM Match */
 
#define DCR2_PCNM   (1U << 1) /* Packet Compress When not Matched */
 
#define DCR2_PCM   (1U << 2) /* Packet Compress When Matched */
 
#define DCR2_PH   (1U << 4) /* Program Hold */
 
#define DCR2_EXPO0   (1U << 12) /* Extended Programmable Output 0 */
 
#define DCR2_EXPO1   (1U << 13) /* Extended Programmable Output 1 */
 
#define DCR2_EXPO2   (1U << 14) /* Extended Programmable Output 2 */
 
#define DCR2_EXPO3   (1U << 15) /* Extended Programmable Output 3 */
 
#define SONIC_NREGS   0x40
 

Functions

struct sonic_rda16 __attribute__ ((__packed__))
 

Variables

uint16_t rda_status
 
uint16_t rda_bytecount
 
uint16_t rda_pkt_ptr0
 
uint16_t rda_pkt_ptr1
 
uint16_t rda_seqno
 
uint16_t rda_link
 
uint16_t rda_inuse
 
uint16_t rra_ptr0
 
uint16_t rra_ptr1
 
uint16_t rra_wc0
 
uint16_t rra_wc1
 
uint16_t frag_ptr0
 
uint16_t frag_ptr1
 
uint16_t frag_size
 
uint16_t tda_status
 
uint16_t tda_pktconfig
 
uint16_t tda_pktsize
 
uint16_t tda_fragcnt
 
struct sonic_frag16 tda_frags [SONIC_NTXFRAGS+1]
 
uint16_t cda_entry
 
uint16_t cda_addr0
 
uint16_t cda_addr1
 
uint16_t cda_addr2
 

Macro Definition Documentation

◆ __attribute__

#define __attribute__ (   x)    /* */

Definition at line 16 of file dp83932reg.h.

◆ __noreturn__

#define __noreturn__   /* */

Definition at line 17 of file dp83932reg.h.

◆ CR_HTX

#define CR_HTX   (1U << 0) /* Halt Transmission */

Definition at line 185 of file dp83932reg.h.

◆ CR_LCAM

#define CR_LCAM   (1U << 9) /* Load CAM */

Definition at line 193 of file dp83932reg.h.

◆ CR_RRRA

#define CR_RRRA   (1U << 8) /* Read RRA */

Definition at line 192 of file dp83932reg.h.

◆ CR_RST

#define CR_RST   (1U << 7) /* Software Reset */

Definition at line 191 of file dp83932reg.h.

◆ CR_RXDIS

#define CR_RXDIS   (1U << 2) /* Receiver Disable */

Definition at line 187 of file dp83932reg.h.

◆ CR_RXEN

#define CR_RXEN   (1U << 3) /* Receiver Enable */

Definition at line 188 of file dp83932reg.h.

◆ CR_ST

#define CR_ST   (1U << 5) /* Start Timer */

Definition at line 190 of file dp83932reg.h.

◆ CR_STP

#define CR_STP   (1U << 4) /* Stop Timer */

Definition at line 189 of file dp83932reg.h.

◆ CR_TXP

#define CR_TXP   (1U << 1) /* Transmit Packets */

Definition at line 186 of file dp83932reg.h.

◆ DCR2_EXPO0

#define DCR2_EXPO0   (1U << 12) /* Extended Programmable Output 0 */

Definition at line 353 of file dp83932reg.h.

◆ DCR2_EXPO1

#define DCR2_EXPO1   (1U << 13) /* Extended Programmable Output 1 */

Definition at line 354 of file dp83932reg.h.

◆ DCR2_EXPO2

#define DCR2_EXPO2   (1U << 14) /* Extended Programmable Output 2 */

Definition at line 355 of file dp83932reg.h.

◆ DCR2_EXPO3

#define DCR2_EXPO3   (1U << 15) /* Extended Programmable Output 3 */

Definition at line 356 of file dp83932reg.h.

◆ DCR2_PCM

#define DCR2_PCM   (1U << 2) /* Packet Compress When Matched */

Definition at line 351 of file dp83932reg.h.

◆ DCR2_PCNM

#define DCR2_PCNM   (1U << 1) /* Packet Compress When not Matched */

Definition at line 350 of file dp83932reg.h.

◆ DCR2_PH

#define DCR2_PH   (1U << 4) /* Program Hold */

Definition at line 352 of file dp83932reg.h.

◆ DCR2_RJCM

#define DCR2_RJCM   (1U << 0) /* Reject on CAM Match */

Definition at line 349 of file dp83932reg.h.

◆ DCR_BMS

#define DCR_BMS   (1U << 4) /* Block Mode Select for DMA */

Definition at line 200 of file dp83932reg.h.

◆ DCR_DW

#define DCR_DW   (1U << 5) /* Data Width Select */

Definition at line 201 of file dp83932reg.h.

◆ DCR_EXBUS

#define DCR_EXBUS   (1U << 15) /* Extended Bus Mode */

Definition at line 210 of file dp83932reg.h.

◆ DCR_LBR

#define DCR_LBR   (1U << 13) /* Latched Bus Retry */

Definition at line 209 of file dp83932reg.h.

◆ DCR_PO0

#define DCR_PO0   (1U << 11) /* Programmable Output 0 */

Definition at line 207 of file dp83932reg.h.

◆ DCR_PO1

#define DCR_PO1   (1U << 12) /* Programmable Output 1 */

Definition at line 208 of file dp83932reg.h.

◆ DCR_RFT0

#define DCR_RFT0   (1U << 2) /* Receive FIFO Threshold (lo) */

Definition at line 198 of file dp83932reg.h.

◆ DCR_RFT1

#define DCR_RFT1   (1U << 3) /* Receive FIFO Threshold (hi) */

Definition at line 199 of file dp83932reg.h.

◆ DCR_SBUS

#define DCR_SBUS   (1U << 10) /* Synchronous Bus Mode */

Definition at line 206 of file dp83932reg.h.

◆ DCR_TFT0

#define DCR_TFT0   (1U << 0) /* Transmit FIFO Threshold (lo) */

Definition at line 196 of file dp83932reg.h.

◆ DCR_TFT1

#define DCR_TFT1   (1U << 1) /* Transmit FIFO Threshold (hi) */

Definition at line 197 of file dp83932reg.h.

◆ DCR_USR0

#define DCR_USR0   (1U << 8) /* User Definable Pin 0 */

Definition at line 204 of file dp83932reg.h.

◆ DCR_USR1

#define DCR_USR1   (1U << 9) /* User Definable Pin 1 */

Definition at line 205 of file dp83932reg.h.

◆ DCR_WC0

#define DCR_WC0   (1U << 6) /* Wait State Control (lo) */

Definition at line 202 of file dp83932reg.h.

◆ DCR_WC1

#define DCR_WC1   (1U << 7) /* Wait State Control (hi) */

Definition at line 203 of file dp83932reg.h.

◆ IMR_BR

#define IMR_BR   (1U << 14) /* Bus Retry Occurred */

Definition at line 261 of file dp83932reg.h.

◆ IMR_CRC

#define IMR_CRC   (1U << 3) /* CRC Tally */

Definition at line 250 of file dp83932reg.h.

◆ IMR_FAE

#define IMR_FAE   (1U << 2) /* Frame Alignment Error Tally */

Definition at line 249 of file dp83932reg.h.

◆ IMR_HBL

#define IMR_HBL   (1U << 13) /* Heartbeat Lost */

Definition at line 260 of file dp83932reg.h.

◆ IMR_LCD

#define IMR_LCD   (1U << 12) /* Load CAM Done */

Definition at line 259 of file dp83932reg.h.

◆ IMR_MP

#define IMR_MP   (1U << 1) /* Missed Packet Tally */

Definition at line 248 of file dp83932reg.h.

◆ IMR_PINT

#define IMR_PINT   (1U << 11) /* Programmable Interrupt */

Definition at line 258 of file dp83932reg.h.

◆ IMR_PRX

#define IMR_PRX   (1U << 10) /* Packet Received */

Definition at line 257 of file dp83932reg.h.

◆ IMR_PTX

#define IMR_PTX   (1U << 9) /* Transmit OK */

Definition at line 256 of file dp83932reg.h.

◆ IMR_RBA

#define IMR_RBA   (1U << 4) /* RBA Exceeded */

Definition at line 251 of file dp83932reg.h.

◆ IMR_RBE

#define IMR_RBE   (1U << 5) /* Rx Buffers Exhausted */

Definition at line 252 of file dp83932reg.h.

◆ IMR_RDE

#define IMR_RDE   (1U << 6) /* Rx Descriptors Exhausted */

Definition at line 253 of file dp83932reg.h.

◆ IMR_RFO

#define IMR_RFO   (1U << 0) /* Rx FIFO Overrun */

Definition at line 247 of file dp83932reg.h.

◆ IMR_TC

#define IMR_TC   (1U << 7) /* Timer Complete */

Definition at line 254 of file dp83932reg.h.

◆ IMR_TXER

#define IMR_TXER   (1U << 8) /* Transmit Error */

Definition at line 255 of file dp83932reg.h.

◆ RCR_AMC

#define RCR_AMC   (1U << 11) /* Accept All Multicast Packets */

Definition at line 224 of file dp83932reg.h.

◆ RCR_BC

#define RCR_BC   (1U << 7) /* Broadcast Packet Received */

Definition at line 220 of file dp83932reg.h.

◆ RCR_BRD

#define RCR_BRD   (1U << 13) /* Accept Broadcast Packets */

Definition at line 226 of file dp83932reg.h.

◆ RCR_COL

#define RCR_COL   (1U << 4) /* Collision Activity */

Definition at line 217 of file dp83932reg.h.

◆ RCR_CRCR

#define RCR_CRCR   (1U << 3) /* CRC Error */

Definition at line 216 of file dp83932reg.h.

◆ RCR_CRS

#define RCR_CRS   (1U << 5) /* Carrier Sense Activity */

Definition at line 218 of file dp83932reg.h.

◆ RCR_ERR

#define RCR_ERR   (1U << 15) /* Accept Packets with Errors */

Definition at line 228 of file dp83932reg.h.

◆ RCR_FAER

#define RCR_FAER   (1U << 2) /* Frame Alignment Error */

Definition at line 215 of file dp83932reg.h.

◆ RCR_LB0

#define RCR_LB0   (1U << 9) /* Loopback Control 0 */

Definition at line 222 of file dp83932reg.h.

◆ RCR_LB1

#define RCR_LB1   (1U << 10) /* Loopback Control 1 */

Definition at line 223 of file dp83932reg.h.

◆ RCR_LBK

#define RCR_LBK   (1U << 1) /* Loopback Packet Received */

Definition at line 214 of file dp83932reg.h.

◆ RCR_LPKT

#define RCR_LPKT   (1U << 6) /* Last Packet in RBA */

Definition at line 219 of file dp83932reg.h.

◆ RCR_MC

#define RCR_MC   (1U << 8) /* Multicast Packet Received */

Definition at line 221 of file dp83932reg.h.

◆ RCR_PRO

#define RCR_PRO   (1U << 12) /* Physical Promiscuous Packets */

Definition at line 225 of file dp83932reg.h.

◆ RCR_PRX

#define RCR_PRX   (1U << 0) /* Packet Received OK */

Definition at line 213 of file dp83932reg.h.

◆ RCR_RNT

#define RCR_RNT   (1U << 14) /* Accept Runt Packets */

Definition at line 227 of file dp83932reg.h.

◆ RDA_LINK_EOL

#define RDA_LINK_EOL   0x01 /* end-of-list */

Definition at line 86 of file dp83932reg.h.

◆ RDA_SEQNO_RBA

#define RDA_SEQNO_RBA (   x)    (((x) >> 8) & 0xff)

Definition at line 83 of file dp83932reg.h.

◆ RDA_SEQNO_RSN

#define RDA_SEQNO_RSN (   x)    ((x) & 0xff)

Definition at line 84 of file dp83932reg.h.

◆ SONIC_ADDR0

#define SONIC_ADDR0   0x1d /* Address Generator 0 */

Definition at line 312 of file dp83932reg.h.

◆ SONIC_ADDR1

#define SONIC_ADDR1   0x1e /* Address Generator 1 */

Definition at line 314 of file dp83932reg.h.

◆ SONIC_CAP0

#define SONIC_CAP0   0x24 /* CAM Address Port 0 */

Definition at line 326 of file dp83932reg.h.

◆ SONIC_CAP1

#define SONIC_CAP1   0x23 /* CAM Address Port 1 */

Definition at line 324 of file dp83932reg.h.

◆ SONIC_CAP2

#define SONIC_CAP2   0x22 /* CAM Address Port 2 */

Definition at line 322 of file dp83932reg.h.

◆ SONIC_CDC

#define SONIC_CDC   0x27 /* CAM Descriptor Count */

Definition at line 332 of file dp83932reg.h.

◆ SONIC_CDP

#define SONIC_CDP   0x26 /* CAM Descriptor Pointer */

Definition at line 330 of file dp83932reg.h.

◆ SONIC_CEP

#define SONIC_CEP   0x21 /* CAM Entry Pointer */

Definition at line 320 of file dp83932reg.h.

◆ SONIC_CER

#define SONIC_CER   0x25 /* CAM Enable Register */

Definition at line 328 of file dp83932reg.h.

◆ SONIC_CR

#define SONIC_CR   0x00 /* Command Register */

Definition at line 184 of file dp83932reg.h.

◆ SONIC_CRBA0

#define SONIC_CRBA0   0x0f /* Current Receive Buffer Address (lo) */

Definition at line 284 of file dp83932reg.h.

◆ SONIC_CRBA1

#define SONIC_CRBA1   0x10 /* Current Receive Buffer Address (hi) */

Definition at line 286 of file dp83932reg.h.

◆ SONIC_CRCETC

#define SONIC_CRCETC   0x2c /* CRC Error Tally Count */

Definition at line 342 of file dp83932reg.h.

◆ SONIC_CRDAR

#define SONIC_CRDAR   0x0e /* Current Rx Descriptor Address Register */

Definition at line 282 of file dp83932reg.h.

◆ SONIC_CTDAR

#define SONIC_CTDAR   0x07 /* Current Tx Descriptor Address Register */

Definition at line 268 of file dp83932reg.h.

◆ SONIC_DCR

#define SONIC_DCR   0x01 /* Data Configuration Register */

Definition at line 195 of file dp83932reg.h.

◆ SONIC_DCR2

#define SONIC_DCR2   0x3f /* Data Configuration Register 2 */

Definition at line 348 of file dp83932reg.h.

◆ SONIC_EOBC

#define SONIC_EOBC   0x13 /* End Of Buffer Word Count */

Definition at line 292 of file dp83932reg.h.

◆ SONIC_FAET

#define SONIC_FAET   0x2d /* Frame Alignment Error Tally */

Definition at line 344 of file dp83932reg.h.

◆ SONIC_IMR

#define SONIC_IMR   0x04 /* Interrupt Mask Register */

Definition at line 246 of file dp83932reg.h.

◆ SONIC_ISR

#define SONIC_ISR   0x05 /* Interrupt Status Register */

Definition at line 263 of file dp83932reg.h.

◆ SONIC_LLFA

#define SONIC_LLFA   0x1f /* Last Link Field Address */

Definition at line 316 of file dp83932reg.h.

◆ SONIC_MPT

#define SONIC_MPT   0x2e /* Missed Packet Tally */

Definition at line 346 of file dp83932reg.h.

◆ SONIC_NREGS

#define SONIC_NREGS   0x40

Definition at line 358 of file dp83932reg.h.

◆ SONIC_NTXFRAGS

#define SONIC_NTXFRAGS   16

Definition at line 115 of file dp83932reg.h.

◆ SONIC_RBWC0

#define SONIC_RBWC0   0x11 /* Remaining Buffer Word Count 0 */

Definition at line 288 of file dp83932reg.h.

◆ SONIC_RBWC1

#define SONIC_RBWC1   0x12 /* Remaining Buffer Word Count 1 */

Definition at line 290 of file dp83932reg.h.

◆ SONIC_RCR

#define SONIC_RCR   0x02 /* Receive Control Register */

Definition at line 212 of file dp83932reg.h.

◆ SONIC_REAR

#define SONIC_REAR   0x16 /* Resource End Address Register */

Definition at line 298 of file dp83932reg.h.

◆ SONIC_RRR

#define SONIC_RRR   0x17 /* Resource Read Register */

Definition at line 300 of file dp83932reg.h.

◆ SONIC_RSAR

#define SONIC_RSAR   0x15 /* Resource Start Address Register */

Definition at line 296 of file dp83932reg.h.

◆ SONIC_RSC

#define SONIC_RSC   0x2b /* Receive Sequence Counter */

Definition at line 340 of file dp83932reg.h.

◆ SONIC_RWR

#define SONIC_RWR   0x18 /* Resource Write Register */

Definition at line 302 of file dp83932reg.h.

◆ SONIC_SRR

#define SONIC_SRR   0x28 /* Silicon Revision Register */

Definition at line 334 of file dp83932reg.h.

◆ SONIC_TBWC0

#define SONIC_TBWC0   0x1b /* Temporary Buffer Word Count 0 */

Definition at line 308 of file dp83932reg.h.

◆ SONIC_TBWC1

#define SONIC_TBWC1   0x1c /* Temporary Buffer Word Count 1 */

Definition at line 310 of file dp83932reg.h.

◆ SONIC_TCR

#define SONIC_TCR   0x03 /* Transmit Control Register */

Definition at line 230 of file dp83932reg.h.

◆ SONIC_TFC

#define SONIC_TFC   0x09 /* Transmit Fragment Count */

Definition at line 272 of file dp83932reg.h.

◆ SONIC_TFS

#define SONIC_TFS   0x0c /* Transmit Fragment Size */

Definition at line 278 of file dp83932reg.h.

◆ SONIC_TPS

#define SONIC_TPS   0x08 /* Transmit Packet Size */

Definition at line 270 of file dp83932reg.h.

◆ SONIC_TRBA0

#define SONIC_TRBA0   0x19 /* Temporary Receive Buffer Address (lo) */

Definition at line 304 of file dp83932reg.h.

◆ SONIC_TRBA1

#define SONIC_TRBA1   0x1a /* Temporary Receive Buffer Address (hi) */

Definition at line 306 of file dp83932reg.h.

◆ SONIC_TSA0

#define SONIC_TSA0   0x0a /* Transmit Start Address (lo) */

Definition at line 274 of file dp83932reg.h.

◆ SONIC_TSA1

#define SONIC_TSA1   0x0b /* Transmit Start Address (hi) */

Definition at line 276 of file dp83932reg.h.

◆ SONIC_TTDA

#define SONIC_TTDA   0x20 /* Temporary Tx Descriptor Address */

Definition at line 318 of file dp83932reg.h.

◆ SONIC_URDAR

#define SONIC_URDAR   0x0d /* Upper Rx Descriptor Address Register */

Definition at line 280 of file dp83932reg.h.

◆ SONIC_URRAR

#define SONIC_URRAR   0x14 /* Upper Rx Resource Address Register */

Definition at line 294 of file dp83932reg.h.

◆ SONIC_UTDAR

#define SONIC_UTDAR   0x06 /* Upper Tx Descriptor Adress Register */

Definition at line 266 of file dp83932reg.h.

◆ SONIC_WT0

#define SONIC_WT0   0x29 /* Watchdog Timer 0 */

Definition at line 336 of file dp83932reg.h.

◆ SONIC_WT1

#define SONIC_WT1   0x2a /* Watchdog Timer 1 */

Definition at line 338 of file dp83932reg.h.

◆ TCR_BCM

#define TCR_BCM   (1U << 1) /* Byte Count Mismatch */

Definition at line 232 of file dp83932reg.h.

◆ TCR_CRCI

#define TCR_CRCI   (1U << 13) /* CRC Inhibit */

Definition at line 242 of file dp83932reg.h.

◆ TCR_CRSL

#define TCR_CRSL   (1U << 7) /* Carrier Sense Lost */

Definition at line 237 of file dp83932reg.h.

◆ TCR_DEF

#define TCR_DEF   (1U << 9) /* Deferred Transmission */

Definition at line 239 of file dp83932reg.h.

◆ TCR_EXC

#define TCR_EXC   (1U << 6) /* Excessive Collisions */

Definition at line 236 of file dp83932reg.h.

◆ TCR_EXD

#define TCR_EXD   (1U << 10) /* Excessive Deferral */

Definition at line 240 of file dp83932reg.h.

◆ TCR_EXDIS

#define TCR_EXDIS   (1U << 12) /* Disable Excessive Deferral Timer */

Definition at line 241 of file dp83932reg.h.

◆ TCR_FU

#define TCR_FU   (1U << 2) /* FIFO Underrun */

Definition at line 233 of file dp83932reg.h.

◆ TCR_NCRS

#define TCR_NCRS   (1U << 8) /* No Carrier Sense */

Definition at line 238 of file dp83932reg.h.

◆ TCR_OWC

#define TCR_OWC   (1U << 5) /* Out of Window Collision */

Definition at line 235 of file dp83932reg.h.

◆ TCR_PINT

#define TCR_PINT   (1U << 15) /* Programmable Interrupt */

Definition at line 244 of file dp83932reg.h.

◆ TCR_PMB

#define TCR_PMB   (1U << 3) /* Packet Monitored Bad */

Definition at line 234 of file dp83932reg.h.

◆ TCR_POWC

#define TCR_POWC   (1U << 14) /* Programmed Out of Window Col. Tmr */

Definition at line 243 of file dp83932reg.h.

◆ TCR_PTX

#define TCR_PTX   (1U << 0) /* Packet Transmitted OK */

Definition at line 231 of file dp83932reg.h.

◆ TDA_LINK_EOL

#define TDA_LINK_EOL   0x01 /* end-of-list */

Definition at line 158 of file dp83932reg.h.

◆ TDA_STATUS_NCOL

#define TDA_STATUS_NCOL (   x)    (((x) >> 11) & 0x1f)

Definition at line 156 of file dp83932reg.h.

Function Documentation

◆ __attribute__()

struct sonic_rda16 __attribute__ ( (__packed__)  )

Variable Documentation

◆ cda_addr0

uint32_t cda_addr0

Definition at line 1 of file dp83932reg.h.

◆ cda_addr1

uint32_t cda_addr1

Definition at line 2 of file dp83932reg.h.

◆ cda_addr2

uint32_t cda_addr2

Definition at line 3 of file dp83932reg.h.

◆ cda_entry

uint32_t cda_entry

Definition at line 0 of file dp83932reg.h.

◆ frag_ptr0

uint32_t frag_ptr0

Definition at line 0 of file dp83932reg.h.

◆ frag_ptr1

uint32_t frag_ptr1

Definition at line 1 of file dp83932reg.h.

◆ frag_size

uint32_t frag_size

Definition at line 2 of file dp83932reg.h.

◆ rda_bytecount

uint32_t rda_bytecount

Definition at line 1 of file dp83932reg.h.

◆ rda_inuse

uint32_t rda_inuse

Definition at line 6 of file dp83932reg.h.

◆ rda_link

uint32_t rda_link

Definition at line 5 of file dp83932reg.h.

◆ rda_pkt_ptr0

uint32_t rda_pkt_ptr0

Definition at line 2 of file dp83932reg.h.

◆ rda_pkt_ptr1

uint32_t rda_pkt_ptr1

Definition at line 3 of file dp83932reg.h.

◆ rda_seqno

uint32_t rda_seqno

Definition at line 4 of file dp83932reg.h.

◆ rda_status

uint32_t rda_status

Definition at line 0 of file dp83932reg.h.

◆ rra_ptr0

uint32_t rra_ptr0

Definition at line 0 of file dp83932reg.h.

◆ rra_ptr1

uint32_t rra_ptr1

Definition at line 1 of file dp83932reg.h.

◆ rra_wc0

uint32_t rra_wc0

Definition at line 2 of file dp83932reg.h.

◆ rra_wc1

uint32_t rra_wc1

Definition at line 3 of file dp83932reg.h.

◆ tda_fragcnt

uint32_t tda_fragcnt

Definition at line 3 of file dp83932reg.h.

◆ tda_frags

struct sonic_frag32 tda_frags

Definition at line 3 of file dp83932reg.h.

◆ tda_pktconfig

uint32_t tda_pktconfig

Definition at line 1 of file dp83932reg.h.

◆ tda_pktsize

uint32_t tda_pktsize

Definition at line 2 of file dp83932reg.h.

◆ tda_status

uint32_t tda_status

Definition at line 0 of file dp83932reg.h.


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