dc21285reg.h File Reference

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Macros
dc21285reg.h File Reference

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Macros

#define VENDOR_ID   0x00
 
#define DC21285_VENDOR_ID   0x1011
 
#define DEVICE_ID   0x02
 
#define DC21285_DEVICE_ID   0x1065
 
#define REVISION   0x08
 
#define CLASS   0x0A
 
#define OUTBOUND_INT_STATUS   0x030
 
#define OUTBOUND_INT_MASK   0x034
 
#define I2O_INBOUND_FIFO   0x040
 
#define I2O_OUTBOUND_FIFO   0x044
 
#define MAILBOX_0   0x050
 
#define MAILBOX_1   0x054
 
#define MAILBOX_2   0x058
 
#define MAILBOX_3   0x05C
 
#define DOORBELL   0x060
 
#define DOORBELL_SETUP   0x064
 
#define ROM_WRITE_BYTE_ADDRESS   0x068
 
#define DMA_CHAN_1_BYTE_COUNT   0x80
 
#define DMA_CHAN_1_PCI_ADDR   0x84
 
#define DMA_CHAN_1_SDRAM_ADDR   0x88
 
#define DMA_CHAN_1_DESCRIPT   0x8C
 
#define DMA_CHAN_1_CONTROL   0x90
 
#define DMA_CHAN_2_BYTE_COUNT   0xA0
 
#define DMA_CHAN_2_PCI_ADDR   0xA4
 
#define DMA_CHAN_2_SDRAM_ADDR   0xA8
 
#define DMA_CHAN_2_DESCRIPTOR   0xAC
 
#define DMA_CHAN_2_CONTROL   0xB0
 
#define DMA_BYTE_COUNT   0
 
#define DMA_PCI_ADDRESS   4
 
#define DMA_SDRAM_ADDRESS   8
 
#define DMA_NEXT_DESCRIPTOR   12
 
#define DMA_INTERBURST_SHIFT   24
 
#define DMA_PCI_TO_SDRAM   0
 
#define DMA_SDRAM_TO_PCI   (1 << 30)
 
#define DMA_END_CHAIN   (1 << 31)
 
#define DMA_ENABLE   (1 << 0)
 
#define DMA_TRANSFER_DONE   (1 << 2)
 
#define DMA_ERROR   (1 << 3)
 
#define DMA_REGISTOR_DESCRIPTOR   (1 << 4)
 
#define DMA_PCI_MEM_READ   (0 << 5)
 
#define DMA_PCI_MEM_READ_LINE   (1 << 5)
 
#define DMA_PCI_MEM_READ_MULTI1   (2 << 5)
 
#define DMA_PCI_MEM_READ_MULTI2   (3 << 5)
 
#define DMA_CHAIN_DONE   (1 << 7)
 
#define DMA_INTERBURST_4   (0 << 8)
 
#define DMA_INTERBURST_8   (1 << 8)
 
#define DMA_INTERBURST_16   (2 << 8)
 
#define DMA_INTERBURST_32   (3 << 8)
 
#define DMA_PCI_LENGTH_8   0
 
#define DMA_PCI_LENGTH_16   (1 << 15)
 
#define DMA_SDRAM_LENGTH_1   (0 << 16)
 
#define DMA_SDRAM_LENGTH_2   (1 << 16)
 
#define DMA_SDRAM_LENGTH_4   (2 << 16)
 
#define DMA_SDRAM_LENGTH_8   (3 << 16)
 
#define DMA_SDRAM_LENGTH_16   (4 << 16)
 
#define CSR_BA_MASK   0x0F8
 
#define CSR_MASK_128B   0x00000000
 
#define CSR_MASK_512KB   0x00040000
 
#define CSR_MASK_1MB   0x000C0000
 
#define CSR_MASK_2MB   0x001C0000
 
#define CSR_MASK_4MB   0x003C0000
 
#define CSR_MASK_8MB   0x007C0000
 
#define CSR_MASK_16MB   0x00FC0000
 
#define CSR_MASK_32MB   0x01FC0000
 
#define CSR_MASK_64MB   0x03FC0000
 
#define CSR_MASK_128MB   0x07FC0000
 
#define CSR_MASK_256MB   0x0FFC0000
 
#define CSR_BA_OFFSET   0x0FC
 
#define SDRAM_BA_MASK   0x100
 
#define SDRAM_MASK_256KB   0x00000000
 
#define SDRAM_MASK_512KB   0x00040000
 
#define SDRAM_MASK_1MB   0x000C0000
 
#define SDRAM_MASK_2MB   0x001C0000
 
#define SDRAM_MASK_4MB   0x003C0000
 
#define SDRAM_MASK_8MB   0x007C0000
 
#define SDRAM_MASK_16MB   0x00FC0000
 
#define SDRAM_MASK_32MB   0x01FC0000
 
#define SDRAM_MASK_64MB   0x03FC0000
 
#define SDRAM_MASK_128MB   0x07FC0000
 
#define SDRAM_MASK_256MB   0x0FFC0000
 
#define SDRAM_WINDOW_DISABLE   (1 << 31)
 
#define SDRAM_BA_OFFSET   0x104
 
#define EXPANSION_ROM_BA_MASK   0x108
 
#define ROM_MASK_1MB   0x00000000
 
#define ROM_MASK_2MB   0x00100000
 
#define ROM_MASK_4MB   0x00300000
 
#define ROM_MASK_8MB   0x00700000
 
#define ROM_MASK_16MB   0x00F00000
 
#define ROM_WINDOW_DISABLE   (1 << 31)
 
#define SDRAM_TIMING   0x10C
 
#define SDRAM_ARRAY_SIZE_0   0x0
 
#define SDRAM_ARRAY_SIZE_1MB   0x1
 
#define SDRAM_ARRAY_SIZE_2MB   0x2
 
#define SDRAM_ARRAY_SIZE_4MB   0x3
 
#define SDRAM_ARRAY_SIZE_8MB   0x4
 
#define SDRAM_ARRAY_SIZE_16MB   0x5
 
#define SDRAM_ARRAY_SIZE_32MB   0x6
 
#define SDRAM_ARRAY_SIZE_64MB   0x7
 
#define SDRAM_2_BANKS   0
 
#define SDRAM_4_BANKS   (1 << 3)
 
#define SDRAM_ADDRESS_MUX_SHIFT   4
 
#define SDRAM_ARRAY_BASE_SHIFT   20
 
#define SDRAM_ADDRESS_SIZE_0   0x110
 
#define SDRAM_ADDRESS_SIZE_1   0x114
 
#define SDRAM_ADDRESS_SIZE_2   0x118
 
#define SDRAM_ADDRESS_SIZE_3   0x11C
 
#define I2O_INBOUND_FREE_HEAD   0x120
 
#define I2O_INBOUND_POST_TAIL   0x124
 
#define I2O_OUTBOUND_POST_HEAD   0x128
 
#define I2O_OUTBOUND_FREE_TAIL   0x12c
 
#define I2O_INBOUND_FREE_COUNT   0x130
 
#define I2O_OUTBOUND_POST_COUNT   0x134
 
#define I2O_INBOUND_POST_COUNT   0x138
 
#define SA_CONTROL   0x13C
 
#define INITIALIZE_COMPLETE   (1 << 0)
 
#define ASSERT_SERR   (1 << 1)
 
#define RECEIVED_SERR   (1 << 3)
 
#define SA_SDRAM_PARITY_ERROR   (1 << 4)
 
#define PCI_SDRAM_PARITY_ERROR   (1 << 5)
 
#define DMA_SDRAM_PARITY_ERROR   (1 << 6)
 
#define DISCARD_TIMER_EXPIRED   (1 << 8)
 
#define PCI_NOT_RESET   (1 << 9)
 
#define WATCHDOG_ENABLE   (1 << 13)
 
#define I2O_SIZE_256   (0 << 10)
 
#define I2O_SIZE_512   (1 << 10)
 
#define I2O_SIZE_1024   (2 << 10)
 
#define I2O_SIZE_2048   (3 << 10)
 
#define I2O_SIZE_4096   (4 << 10)
 
#define I2O_SIZE_8192   (5 << 10)
 
#define I2O_SIZE_16384   (6 << 10)
 
#define I2O_SIZE_32768   (7 << 10)
 
#define ROM_WIDTH_8   (3 << 14)
 
#define ROM_WIDTH_16   (1 << 14)
 
#define ROM_WIDTH_32   (2 << 14)
 
#define ROM_ACCESS_TIME_SHIFT   16
 
#define ROM_BURST_TIME_SHIFT   20
 
#define ROM_TRISTATE_TIME_SHIFT   24
 
#define XCS_DIRECTION_SHIFT   28
 
#define PCI_CENTRAL_FUNCTION   (1 << 31)
 
#define PCI_ADDRESS_EXTENSION   0x140
 
#define PREFETCHABLE_MEM_RANGE   0x144
 
#define XBUS_CYCLE_ARBITER   0x148
 
#define XBUS_CYCLE_0_SHIFT   0
 
#define XBUS_CYCLE_1_SHIFT   3
 
#define XBUS_CYCLE_2_SHIFT   6
 
#define XBUS_CYCLE_3_SHIFT   9
 
#define XBUS_CYCLE_STROBE_SHIFT   12
 
#define XBUS_PCI_ARBITER   (1 << 23)
 
#define XBUS_INT_IN_L0_LOW   0
 
#define XBUS_INT_IN_L0_HIGH   (1 << 24)
 
#define XBUS_INT_IN_L1_LOW   0
 
#define XBUS_INT_IN_L1_HIGH   (1 << 25)
 
#define XBUS_INT_IN_L2_LOW   0
 
#define XBUS_INT_IN_L2_HIGH   (1 << 26)
 
#define XBUS_INT_IN_L3_LOW   0
 
#define XBUS_INT_IN_L3_HIGH   (1 << 27)
 
#define XBUS_INT_XCS0_LOW   0
 
#define XBUS_INT_XCS0_HIGH   (1 << 28)
 
#define XBUS_INT_XCS1_LOW   0
 
#define XBUS_INT_XCS1_HIGH   (1 << 29)
 
#define XBUS_INT_XCS2_LOW   0
 
#define XBUS_INT_XCS2_HIGH   (1 << 30)
 
#define XBUS_PCI_INT_REQUEST   (1 << 31)
 
#define XBUS_IO_STROBE_MASK   0x14C
 
#define XBUS_IO_STROBE_0_SHIFT   0
 
#define XBUS_IO_STROBE_2_SHIFT   8
 
#define XBUS_IO_STROBE_3_SHIFT   16
 
#define XBUS_IO_STROBE_4_SHIFT   24
 
#define DOORBELL_PCI_MASK   0x150
 
#define DOORBELL_SA_MASK   0x154
 
#define UART_DATA   0x160
 
#define UART_RX_STAT   0x164
 
#define UART_PARITY_ERROR   0x01
 
#define UART_FRAME_ERROR   0x02
 
#define UART_OVERRUN_ERROR   0x04
 
#define UART_RX_ERROR
 
#define UART_H_UBRLCR   0x168
 
#define UART_BREAK   0x01
 
#define UART_PARITY_ENABLE   0x02
 
#define UART_ODD_PARITY   0x00
 
#define UART_EVEN_PARITY   0x04
 
#define UART_STOP_BITS_1   0x00
 
#define UART_STOP_BITS_2   0x08
 
#define UART_ENABLE_FIFO   0x10
 
#define UART_DATA_BITS_5   0x00
 
#define UART_DATA_BITS_6   0x20
 
#define UART_DATA_BITS_7   0x40
 
#define UART_DATA_BITS_8   0x60
 
#define UART_M_UBRLCR   0x16C
 
#define UART_L_UBRLCR   0x170
 
#define UART_BRD(fclk, x)   (((fclk) / 4 / 16 / x) - 1)
 
#define UART_CONTROL   0x174
 
#define UART_ENABLE   0x01
 
#define UART_SIR_ENABLE   0x02
 
#define UART_IRDA_ENABLE   0x04
 
#define UART_FLAGS   0x178
 
#define UART_TX_BUSY   0x08
 
#define UART_RX_FULL   0x10
 
#define UART_TX_EMPTY   0x20
 
#define IRQ_RESERVED0   0x00
 
#define IRQ_SOFTINT   0x01
 
#define IRQ_SERIAL_RX   0x02
 
#define IRQ_SERIAL_TX   0x03
 
#define IRQ_TIMER_1   0x04
 
#define IRQ_TIMER_2   0x05
 
#define IRQ_TIMER_3   0x06
 
#define IRQ_TIMER_4   0x07
 
#define IRQ_IN_L0   0x08
 
#define IRQ_IN_L1   0x09
 
#define IRQ_IN_L2   0x0A
 
#define IRQ_IN_L3   0x0B
 
#define IRQ_XCS_L0   0x0C
 
#define IRQ_XCS_L1   0x0D
 
#define IRQ_XCS_L2   0x0E
 
#define IRQ_DOORBELL   0x0F
 
#define IRQ_DMA_1   0x10
 
#define IRQ_DMA_2   0x11
 
#define IRQ_PCI   0x12
 
#define IRQ_PMCSR   0x13
 
#define IRQ_RESERVED1   0x14
 
#define IRQ_RESERVED2   0x15
 
#define IRQ_BIST   0x16
 
#define IRQ_SERR   0x17
 
#define IRQ_SDRAM_PARITY   0x18
 
#define IRQ_I2O   0x19
 
#define IRQ_RESERVED3   0x1A
 
#define IRQ_DISCARD_TIMER   0x1B
 
#define IRQ_DATA_PARITY   0x1C
 
#define IRQ_MASTER_ABORT   0x1D
 
#define IRQ_TARGET_ABORT   0x1E
 
#define IRQ_PARITY   0x1F
 
#define IRQ_STATUS   0x180
 
#define IRQ_RAW_STATUS   0x184
 
#define IRQ_ENABLE   0x188
 
#define IRQ_ENABLE_SET   0x188
 
#define IRQ_ENABLE_CLEAR   0x18c
 
#define IRQ_SOFT   0x190
 
#define FIQ_STATUS   0x280
 
#define FIQ_RAW_STATUS   0x284
 
#define FIQ_ENABLE   0x288
 
#define FIQ_ENABLE_SET   0x288
 
#define FIQ_ENABLE_CLEAR   0x28c
 
#define FIQ_SOFT   0x290
 
#define TIMER_LOAD   0x00
 
#define TIMER_VALUE   0x04
 
#define TIMER_CONTROL   0x08
 
#define TIMER_CLEAR   0x0C
 
#define TIMER_1_BASE   0x300
 
#define TIMER_2_BASE   0x320
 
#define TIMER_3_BASE   0x340
 
#define TIMER_4_BASE   0x360
 
#define TIMER_FCLK   0x00
 
#define TIMER_FCLK_16   0x04
 
#define TIMER_FCLK_256   0x08
 
#define TIMER_EXTERNAL   0x0C
 
#define TIMER_MODE_FREERUN   0x00
 
#define TIMER_MODE_PERIODIC   0x40
 
#define TIMER_ENABLE   0x80
 
#define TIMER_MAX_VAL   0x00FFFFFF
 
#define TIMER_1_LOAD   0x300
 
#define TIMER_1_VALUE   0x304
 
#define TIMER_1_CONTROL   0x308
 
#define TIMER_1_CLEAR   0x30C
 
#define TIMER_2_LOAD   0x320
 
#define TIMER_2_VALUE   0x324
 
#define TIMER_2_CONTROL   0x328
 
#define TIMER_2_CLEAR   0x32C
 
#define TIMER_3_LOAD   0x340
 
#define TIMER_3_VALUE   0x344
 
#define TIMER_3_CONTROL   0x348
 
#define TIMER_3_CLEAR   0x34C
 
#define TIMER_4_LOAD   0x360
 
#define TIMER_4_VALUE   0x364
 
#define TIMER_4_CONTROL   0x368
 
#define TIMER_4_CLEAR   0x36C
 
#define FCLK   50000000
 

Macro Definition Documentation

◆ ASSERT_SERR

#define ASSERT_SERR   (1 << 1)

Definition at line 200 of file dc21285reg.h.

◆ CLASS

#define CLASS   0x0A

Definition at line 53 of file dc21285reg.h.

◆ CSR_BA_MASK

#define CSR_BA_MASK   0x0F8

Definition at line 125 of file dc21285reg.h.

◆ CSR_BA_OFFSET

#define CSR_BA_OFFSET   0x0FC

Definition at line 137 of file dc21285reg.h.

◆ CSR_MASK_128B

#define CSR_MASK_128B   0x00000000

Definition at line 126 of file dc21285reg.h.

◆ CSR_MASK_128MB

#define CSR_MASK_128MB   0x07FC0000

Definition at line 135 of file dc21285reg.h.

◆ CSR_MASK_16MB

#define CSR_MASK_16MB   0x00FC0000

Definition at line 132 of file dc21285reg.h.

◆ CSR_MASK_1MB

#define CSR_MASK_1MB   0x000C0000

Definition at line 128 of file dc21285reg.h.

◆ CSR_MASK_256MB

#define CSR_MASK_256MB   0x0FFC0000

Definition at line 136 of file dc21285reg.h.

◆ CSR_MASK_2MB

#define CSR_MASK_2MB   0x001C0000

Definition at line 129 of file dc21285reg.h.

◆ CSR_MASK_32MB

#define CSR_MASK_32MB   0x01FC0000

Definition at line 133 of file dc21285reg.h.

◆ CSR_MASK_4MB

#define CSR_MASK_4MB   0x003C0000

Definition at line 130 of file dc21285reg.h.

◆ CSR_MASK_512KB

#define CSR_MASK_512KB   0x00040000

Definition at line 127 of file dc21285reg.h.

◆ CSR_MASK_64MB

#define CSR_MASK_64MB   0x03FC0000

Definition at line 134 of file dc21285reg.h.

◆ CSR_MASK_8MB

#define CSR_MASK_8MB   0x007C0000

Definition at line 131 of file dc21285reg.h.

◆ DC21285_DEVICE_ID

#define DC21285_DEVICE_ID   0x1065

Definition at line 51 of file dc21285reg.h.

◆ DC21285_VENDOR_ID

#define DC21285_VENDOR_ID   0x1011

Definition at line 49 of file dc21285reg.h.

◆ DEVICE_ID

#define DEVICE_ID   0x02

Definition at line 50 of file dc21285reg.h.

◆ DISCARD_TIMER_EXPIRED

#define DISCARD_TIMER_EXPIRED   (1 << 8)

Definition at line 205 of file dc21285reg.h.

◆ DMA_BYTE_COUNT

#define DMA_BYTE_COUNT   0

Definition at line 88 of file dc21285reg.h.

◆ DMA_CHAIN_DONE

#define DMA_CHAIN_DONE   (1 << 7)

Definition at line 110 of file dc21285reg.h.

◆ DMA_CHAN_1_BYTE_COUNT

#define DMA_CHAN_1_BYTE_COUNT   0x80

Definition at line 75 of file dc21285reg.h.

◆ DMA_CHAN_1_CONTROL

#define DMA_CHAN_1_CONTROL   0x90

Definition at line 79 of file dc21285reg.h.

◆ DMA_CHAN_1_DESCRIPT

#define DMA_CHAN_1_DESCRIPT   0x8C

Definition at line 78 of file dc21285reg.h.

◆ DMA_CHAN_1_PCI_ADDR

#define DMA_CHAN_1_PCI_ADDR   0x84

Definition at line 76 of file dc21285reg.h.

◆ DMA_CHAN_1_SDRAM_ADDR

#define DMA_CHAN_1_SDRAM_ADDR   0x88

Definition at line 77 of file dc21285reg.h.

◆ DMA_CHAN_2_BYTE_COUNT

#define DMA_CHAN_2_BYTE_COUNT   0xA0

Definition at line 80 of file dc21285reg.h.

◆ DMA_CHAN_2_CONTROL

#define DMA_CHAN_2_CONTROL   0xB0

Definition at line 84 of file dc21285reg.h.

◆ DMA_CHAN_2_DESCRIPTOR

#define DMA_CHAN_2_DESCRIPTOR   0xAC

Definition at line 83 of file dc21285reg.h.

◆ DMA_CHAN_2_PCI_ADDR

#define DMA_CHAN_2_PCI_ADDR   0xA4

Definition at line 81 of file dc21285reg.h.

◆ DMA_CHAN_2_SDRAM_ADDR

#define DMA_CHAN_2_SDRAM_ADDR   0xA8

Definition at line 82 of file dc21285reg.h.

◆ DMA_ENABLE

#define DMA_ENABLE   (1 << 0)

Definition at line 102 of file dc21285reg.h.

◆ DMA_END_CHAIN

#define DMA_END_CHAIN   (1 << 31)

Definition at line 98 of file dc21285reg.h.

◆ DMA_ERROR

#define DMA_ERROR   (1 << 3)

Definition at line 104 of file dc21285reg.h.

◆ DMA_INTERBURST_16

#define DMA_INTERBURST_16   (2 << 8)

Definition at line 113 of file dc21285reg.h.

◆ DMA_INTERBURST_32

#define DMA_INTERBURST_32   (3 << 8)

Definition at line 114 of file dc21285reg.h.

◆ DMA_INTERBURST_4

#define DMA_INTERBURST_4   (0 << 8)

Definition at line 111 of file dc21285reg.h.

◆ DMA_INTERBURST_8

#define DMA_INTERBURST_8   (1 << 8)

Definition at line 112 of file dc21285reg.h.

◆ DMA_INTERBURST_SHIFT

#define DMA_INTERBURST_SHIFT   24

Definition at line 95 of file dc21285reg.h.

◆ DMA_NEXT_DESCRIPTOR

#define DMA_NEXT_DESCRIPTOR   12

Definition at line 91 of file dc21285reg.h.

◆ DMA_PCI_ADDRESS

#define DMA_PCI_ADDRESS   4

Definition at line 89 of file dc21285reg.h.

◆ DMA_PCI_LENGTH_16

#define DMA_PCI_LENGTH_16   (1 << 15)

Definition at line 116 of file dc21285reg.h.

◆ DMA_PCI_LENGTH_8

#define DMA_PCI_LENGTH_8   0

Definition at line 115 of file dc21285reg.h.

◆ DMA_PCI_MEM_READ

#define DMA_PCI_MEM_READ   (0 << 5)

Definition at line 106 of file dc21285reg.h.

◆ DMA_PCI_MEM_READ_LINE

#define DMA_PCI_MEM_READ_LINE   (1 << 5)

Definition at line 107 of file dc21285reg.h.

◆ DMA_PCI_MEM_READ_MULTI1

#define DMA_PCI_MEM_READ_MULTI1   (2 << 5)

Definition at line 108 of file dc21285reg.h.

◆ DMA_PCI_MEM_READ_MULTI2

#define DMA_PCI_MEM_READ_MULTI2   (3 << 5)

Definition at line 109 of file dc21285reg.h.

◆ DMA_PCI_TO_SDRAM

#define DMA_PCI_TO_SDRAM   0

Definition at line 96 of file dc21285reg.h.

◆ DMA_REGISTOR_DESCRIPTOR

#define DMA_REGISTOR_DESCRIPTOR   (1 << 4)

Definition at line 105 of file dc21285reg.h.

◆ DMA_SDRAM_ADDRESS

#define DMA_SDRAM_ADDRESS   8

Definition at line 90 of file dc21285reg.h.

◆ DMA_SDRAM_LENGTH_1

#define DMA_SDRAM_LENGTH_1   (0 << 16)

Definition at line 117 of file dc21285reg.h.

◆ DMA_SDRAM_LENGTH_16

#define DMA_SDRAM_LENGTH_16   (4 << 16)

Definition at line 121 of file dc21285reg.h.

◆ DMA_SDRAM_LENGTH_2

#define DMA_SDRAM_LENGTH_2   (1 << 16)

Definition at line 118 of file dc21285reg.h.

◆ DMA_SDRAM_LENGTH_4

#define DMA_SDRAM_LENGTH_4   (2 << 16)

Definition at line 119 of file dc21285reg.h.

◆ DMA_SDRAM_LENGTH_8

#define DMA_SDRAM_LENGTH_8   (3 << 16)

Definition at line 120 of file dc21285reg.h.

◆ DMA_SDRAM_PARITY_ERROR

#define DMA_SDRAM_PARITY_ERROR   (1 << 6)

Definition at line 204 of file dc21285reg.h.

◆ DMA_SDRAM_TO_PCI

#define DMA_SDRAM_TO_PCI   (1 << 30)

Definition at line 97 of file dc21285reg.h.

◆ DMA_TRANSFER_DONE

#define DMA_TRANSFER_DONE   (1 << 2)

Definition at line 103 of file dc21285reg.h.

◆ DOORBELL

#define DOORBELL   0x060

Definition at line 69 of file dc21285reg.h.

◆ DOORBELL_PCI_MASK

#define DOORBELL_PCI_MASK   0x150

Definition at line 259 of file dc21285reg.h.

◆ DOORBELL_SA_MASK

#define DOORBELL_SA_MASK   0x154

Definition at line 260 of file dc21285reg.h.

◆ DOORBELL_SETUP

#define DOORBELL_SETUP   0x064

Definition at line 70 of file dc21285reg.h.

◆ EXPANSION_ROM_BA_MASK

#define EXPANSION_ROM_BA_MASK   0x108

Definition at line 158 of file dc21285reg.h.

◆ FCLK

#define FCLK   50000000

Definition at line 396 of file dc21285reg.h.

◆ FIQ_ENABLE

#define FIQ_ENABLE   0x288

Definition at line 342 of file dc21285reg.h.

◆ FIQ_ENABLE_CLEAR

#define FIQ_ENABLE_CLEAR   0x28c

Definition at line 344 of file dc21285reg.h.

◆ FIQ_ENABLE_SET

#define FIQ_ENABLE_SET   0x288

Definition at line 343 of file dc21285reg.h.

◆ FIQ_RAW_STATUS

#define FIQ_RAW_STATUS   0x284

Definition at line 341 of file dc21285reg.h.

◆ FIQ_SOFT

#define FIQ_SOFT   0x290

Definition at line 345 of file dc21285reg.h.

◆ FIQ_STATUS

#define FIQ_STATUS   0x280

Definition at line 340 of file dc21285reg.h.

◆ I2O_INBOUND_FIFO

#define I2O_INBOUND_FIFO   0x040

Definition at line 59 of file dc21285reg.h.

◆ I2O_INBOUND_FREE_COUNT

#define I2O_INBOUND_FREE_COUNT   0x130

Definition at line 192 of file dc21285reg.h.

◆ I2O_INBOUND_FREE_HEAD

#define I2O_INBOUND_FREE_HEAD   0x120

Definition at line 188 of file dc21285reg.h.

◆ I2O_INBOUND_POST_COUNT

#define I2O_INBOUND_POST_COUNT   0x138

Definition at line 194 of file dc21285reg.h.

◆ I2O_INBOUND_POST_TAIL

#define I2O_INBOUND_POST_TAIL   0x124

Definition at line 189 of file dc21285reg.h.

◆ I2O_OUTBOUND_FIFO

#define I2O_OUTBOUND_FIFO   0x044

Definition at line 60 of file dc21285reg.h.

◆ I2O_OUTBOUND_FREE_TAIL

#define I2O_OUTBOUND_FREE_TAIL   0x12c

Definition at line 191 of file dc21285reg.h.

◆ I2O_OUTBOUND_POST_COUNT

#define I2O_OUTBOUND_POST_COUNT   0x134

Definition at line 193 of file dc21285reg.h.

◆ I2O_OUTBOUND_POST_HEAD

#define I2O_OUTBOUND_POST_HEAD   0x128

Definition at line 190 of file dc21285reg.h.

◆ I2O_SIZE_1024

#define I2O_SIZE_1024   (2 << 10)

Definition at line 210 of file dc21285reg.h.

◆ I2O_SIZE_16384

#define I2O_SIZE_16384   (6 << 10)

Definition at line 214 of file dc21285reg.h.

◆ I2O_SIZE_2048

#define I2O_SIZE_2048   (3 << 10)

Definition at line 211 of file dc21285reg.h.

◆ I2O_SIZE_256

#define I2O_SIZE_256   (0 << 10)

Definition at line 208 of file dc21285reg.h.

◆ I2O_SIZE_32768

#define I2O_SIZE_32768   (7 << 10)

Definition at line 215 of file dc21285reg.h.

◆ I2O_SIZE_4096

#define I2O_SIZE_4096   (4 << 10)

Definition at line 212 of file dc21285reg.h.

◆ I2O_SIZE_512

#define I2O_SIZE_512   (1 << 10)

Definition at line 209 of file dc21285reg.h.

◆ I2O_SIZE_8192

#define I2O_SIZE_8192   (5 << 10)

Definition at line 213 of file dc21285reg.h.

◆ INITIALIZE_COMPLETE

#define INITIALIZE_COMPLETE   (1 << 0)

Definition at line 199 of file dc21285reg.h.

◆ IRQ_BIST

#define IRQ_BIST   0x16

Definition at line 320 of file dc21285reg.h.

◆ IRQ_DATA_PARITY

#define IRQ_DATA_PARITY   0x1C

Definition at line 326 of file dc21285reg.h.

◆ IRQ_DISCARD_TIMER

#define IRQ_DISCARD_TIMER   0x1B

Definition at line 325 of file dc21285reg.h.

◆ IRQ_DMA_1

#define IRQ_DMA_1   0x10

Definition at line 314 of file dc21285reg.h.

◆ IRQ_DMA_2

#define IRQ_DMA_2   0x11

Definition at line 315 of file dc21285reg.h.

◆ IRQ_DOORBELL

#define IRQ_DOORBELL   0x0F

Definition at line 313 of file dc21285reg.h.

◆ IRQ_ENABLE

#define IRQ_ENABLE   0x188

Definition at line 335 of file dc21285reg.h.

◆ IRQ_ENABLE_CLEAR

#define IRQ_ENABLE_CLEAR   0x18c

Definition at line 337 of file dc21285reg.h.

◆ IRQ_ENABLE_SET

#define IRQ_ENABLE_SET   0x188

Definition at line 336 of file dc21285reg.h.

◆ IRQ_I2O

#define IRQ_I2O   0x19

Definition at line 323 of file dc21285reg.h.

◆ IRQ_IN_L0

#define IRQ_IN_L0   0x08

Definition at line 306 of file dc21285reg.h.

◆ IRQ_IN_L1

#define IRQ_IN_L1   0x09

Definition at line 307 of file dc21285reg.h.

◆ IRQ_IN_L2

#define IRQ_IN_L2   0x0A

Definition at line 308 of file dc21285reg.h.

◆ IRQ_IN_L3

#define IRQ_IN_L3   0x0B

Definition at line 309 of file dc21285reg.h.

◆ IRQ_MASTER_ABORT

#define IRQ_MASTER_ABORT   0x1D

Definition at line 327 of file dc21285reg.h.

◆ IRQ_PARITY

#define IRQ_PARITY   0x1F

Definition at line 329 of file dc21285reg.h.

◆ IRQ_PCI

#define IRQ_PCI   0x12

Definition at line 316 of file dc21285reg.h.

◆ IRQ_PMCSR

#define IRQ_PMCSR   0x13

Definition at line 317 of file dc21285reg.h.

◆ IRQ_RAW_STATUS

#define IRQ_RAW_STATUS   0x184

Definition at line 334 of file dc21285reg.h.

◆ IRQ_RESERVED0

#define IRQ_RESERVED0   0x00

Definition at line 298 of file dc21285reg.h.

◆ IRQ_RESERVED1

#define IRQ_RESERVED1   0x14

Definition at line 318 of file dc21285reg.h.

◆ IRQ_RESERVED2

#define IRQ_RESERVED2   0x15

Definition at line 319 of file dc21285reg.h.

◆ IRQ_RESERVED3

#define IRQ_RESERVED3   0x1A

Definition at line 324 of file dc21285reg.h.

◆ IRQ_SDRAM_PARITY

#define IRQ_SDRAM_PARITY   0x18

Definition at line 322 of file dc21285reg.h.

◆ IRQ_SERIAL_RX

#define IRQ_SERIAL_RX   0x02

Definition at line 300 of file dc21285reg.h.

◆ IRQ_SERIAL_TX

#define IRQ_SERIAL_TX   0x03

Definition at line 301 of file dc21285reg.h.

◆ IRQ_SERR

#define IRQ_SERR   0x17

Definition at line 321 of file dc21285reg.h.

◆ IRQ_SOFT

#define IRQ_SOFT   0x190

Definition at line 338 of file dc21285reg.h.

◆ IRQ_SOFTINT

#define IRQ_SOFTINT   0x01

Definition at line 299 of file dc21285reg.h.

◆ IRQ_STATUS

#define IRQ_STATUS   0x180

Definition at line 333 of file dc21285reg.h.

◆ IRQ_TARGET_ABORT

#define IRQ_TARGET_ABORT   0x1E

Definition at line 328 of file dc21285reg.h.

◆ IRQ_TIMER_1

#define IRQ_TIMER_1   0x04

Definition at line 302 of file dc21285reg.h.

◆ IRQ_TIMER_2

#define IRQ_TIMER_2   0x05

Definition at line 303 of file dc21285reg.h.

◆ IRQ_TIMER_3

#define IRQ_TIMER_3   0x06

Definition at line 304 of file dc21285reg.h.

◆ IRQ_TIMER_4

#define IRQ_TIMER_4   0x07

Definition at line 305 of file dc21285reg.h.

◆ IRQ_XCS_L0

#define IRQ_XCS_L0   0x0C

Definition at line 310 of file dc21285reg.h.

◆ IRQ_XCS_L1

#define IRQ_XCS_L1   0x0D

Definition at line 311 of file dc21285reg.h.

◆ IRQ_XCS_L2

#define IRQ_XCS_L2   0x0E

Definition at line 312 of file dc21285reg.h.

◆ MAILBOX_0

#define MAILBOX_0   0x050

Definition at line 64 of file dc21285reg.h.

◆ MAILBOX_1

#define MAILBOX_1   0x054

Definition at line 65 of file dc21285reg.h.

◆ MAILBOX_2

#define MAILBOX_2   0x058

Definition at line 66 of file dc21285reg.h.

◆ MAILBOX_3

#define MAILBOX_3   0x05C

Definition at line 67 of file dc21285reg.h.

◆ OUTBOUND_INT_MASK

#define OUTBOUND_INT_MASK   0x034

Definition at line 58 of file dc21285reg.h.

◆ OUTBOUND_INT_STATUS

#define OUTBOUND_INT_STATUS   0x030

Definition at line 57 of file dc21285reg.h.

◆ PCI_ADDRESS_EXTENSION

#define PCI_ADDRESS_EXTENSION   0x140

Definition at line 225 of file dc21285reg.h.

◆ PCI_CENTRAL_FUNCTION

#define PCI_CENTRAL_FUNCTION   (1 << 31)

Definition at line 223 of file dc21285reg.h.

◆ PCI_NOT_RESET

#define PCI_NOT_RESET   (1 << 9)

Definition at line 206 of file dc21285reg.h.

◆ PCI_SDRAM_PARITY_ERROR

#define PCI_SDRAM_PARITY_ERROR   (1 << 5)

Definition at line 203 of file dc21285reg.h.

◆ PREFETCHABLE_MEM_RANGE

#define PREFETCHABLE_MEM_RANGE   0x144

Definition at line 226 of file dc21285reg.h.

◆ RECEIVED_SERR

#define RECEIVED_SERR   (1 << 3)

Definition at line 201 of file dc21285reg.h.

◆ REVISION

#define REVISION   0x08

Definition at line 52 of file dc21285reg.h.

◆ ROM_ACCESS_TIME_SHIFT

#define ROM_ACCESS_TIME_SHIFT   16

Definition at line 219 of file dc21285reg.h.

◆ ROM_BURST_TIME_SHIFT

#define ROM_BURST_TIME_SHIFT   20

Definition at line 220 of file dc21285reg.h.

◆ ROM_MASK_16MB

#define ROM_MASK_16MB   0x00F00000

Definition at line 163 of file dc21285reg.h.

◆ ROM_MASK_1MB

#define ROM_MASK_1MB   0x00000000

Definition at line 159 of file dc21285reg.h.

◆ ROM_MASK_2MB

#define ROM_MASK_2MB   0x00100000

Definition at line 160 of file dc21285reg.h.

◆ ROM_MASK_4MB

#define ROM_MASK_4MB   0x00300000

Definition at line 161 of file dc21285reg.h.

◆ ROM_MASK_8MB

#define ROM_MASK_8MB   0x00700000

Definition at line 162 of file dc21285reg.h.

◆ ROM_TRISTATE_TIME_SHIFT

#define ROM_TRISTATE_TIME_SHIFT   24

Definition at line 221 of file dc21285reg.h.

◆ ROM_WIDTH_16

#define ROM_WIDTH_16   (1 << 14)

Definition at line 217 of file dc21285reg.h.

◆ ROM_WIDTH_32

#define ROM_WIDTH_32   (2 << 14)

Definition at line 218 of file dc21285reg.h.

◆ ROM_WIDTH_8

#define ROM_WIDTH_8   (3 << 14)

Definition at line 216 of file dc21285reg.h.

◆ ROM_WINDOW_DISABLE

#define ROM_WINDOW_DISABLE   (1 << 31)

Definition at line 164 of file dc21285reg.h.

◆ ROM_WRITE_BYTE_ADDRESS

#define ROM_WRITE_BYTE_ADDRESS   0x068

Definition at line 71 of file dc21285reg.h.

◆ SA_CONTROL

#define SA_CONTROL   0x13C

Definition at line 198 of file dc21285reg.h.

◆ SA_SDRAM_PARITY_ERROR

#define SA_SDRAM_PARITY_ERROR   (1 << 4)

Definition at line 202 of file dc21285reg.h.

◆ SDRAM_2_BANKS

#define SDRAM_2_BANKS   0

Definition at line 177 of file dc21285reg.h.

◆ SDRAM_4_BANKS

#define SDRAM_4_BANKS   (1 << 3)

Definition at line 178 of file dc21285reg.h.

◆ SDRAM_ADDRESS_MUX_SHIFT

#define SDRAM_ADDRESS_MUX_SHIFT   4

Definition at line 179 of file dc21285reg.h.

◆ SDRAM_ADDRESS_SIZE_0

#define SDRAM_ADDRESS_SIZE_0   0x110

Definition at line 181 of file dc21285reg.h.

◆ SDRAM_ADDRESS_SIZE_1

#define SDRAM_ADDRESS_SIZE_1   0x114

Definition at line 182 of file dc21285reg.h.

◆ SDRAM_ADDRESS_SIZE_2

#define SDRAM_ADDRESS_SIZE_2   0x118

Definition at line 183 of file dc21285reg.h.

◆ SDRAM_ADDRESS_SIZE_3

#define SDRAM_ADDRESS_SIZE_3   0x11C

Definition at line 184 of file dc21285reg.h.

◆ SDRAM_ARRAY_BASE_SHIFT

#define SDRAM_ARRAY_BASE_SHIFT   20

Definition at line 180 of file dc21285reg.h.

◆ SDRAM_ARRAY_SIZE_0

#define SDRAM_ARRAY_SIZE_0   0x0

Definition at line 169 of file dc21285reg.h.

◆ SDRAM_ARRAY_SIZE_16MB

#define SDRAM_ARRAY_SIZE_16MB   0x5

Definition at line 174 of file dc21285reg.h.

◆ SDRAM_ARRAY_SIZE_1MB

#define SDRAM_ARRAY_SIZE_1MB   0x1

Definition at line 170 of file dc21285reg.h.

◆ SDRAM_ARRAY_SIZE_2MB

#define SDRAM_ARRAY_SIZE_2MB   0x2

Definition at line 171 of file dc21285reg.h.

◆ SDRAM_ARRAY_SIZE_32MB

#define SDRAM_ARRAY_SIZE_32MB   0x6

Definition at line 175 of file dc21285reg.h.

◆ SDRAM_ARRAY_SIZE_4MB

#define SDRAM_ARRAY_SIZE_4MB   0x3

Definition at line 172 of file dc21285reg.h.

◆ SDRAM_ARRAY_SIZE_64MB

#define SDRAM_ARRAY_SIZE_64MB   0x7

Definition at line 176 of file dc21285reg.h.

◆ SDRAM_ARRAY_SIZE_8MB

#define SDRAM_ARRAY_SIZE_8MB   0x4

Definition at line 173 of file dc21285reg.h.

◆ SDRAM_BA_MASK

#define SDRAM_BA_MASK   0x100

Definition at line 141 of file dc21285reg.h.

◆ SDRAM_BA_OFFSET

#define SDRAM_BA_OFFSET   0x104

Definition at line 154 of file dc21285reg.h.

◆ SDRAM_MASK_128MB

#define SDRAM_MASK_128MB   0x07FC0000

Definition at line 151 of file dc21285reg.h.

◆ SDRAM_MASK_16MB

#define SDRAM_MASK_16MB   0x00FC0000

Definition at line 148 of file dc21285reg.h.

◆ SDRAM_MASK_1MB

#define SDRAM_MASK_1MB   0x000C0000

Definition at line 144 of file dc21285reg.h.

◆ SDRAM_MASK_256KB

#define SDRAM_MASK_256KB   0x00000000

Definition at line 142 of file dc21285reg.h.

◆ SDRAM_MASK_256MB

#define SDRAM_MASK_256MB   0x0FFC0000

Definition at line 152 of file dc21285reg.h.

◆ SDRAM_MASK_2MB

#define SDRAM_MASK_2MB   0x001C0000

Definition at line 145 of file dc21285reg.h.

◆ SDRAM_MASK_32MB

#define SDRAM_MASK_32MB   0x01FC0000

Definition at line 149 of file dc21285reg.h.

◆ SDRAM_MASK_4MB

#define SDRAM_MASK_4MB   0x003C0000

Definition at line 146 of file dc21285reg.h.

◆ SDRAM_MASK_512KB

#define SDRAM_MASK_512KB   0x00040000

Definition at line 143 of file dc21285reg.h.

◆ SDRAM_MASK_64MB

#define SDRAM_MASK_64MB   0x03FC0000

Definition at line 150 of file dc21285reg.h.

◆ SDRAM_MASK_8MB

#define SDRAM_MASK_8MB   0x007C0000

Definition at line 147 of file dc21285reg.h.

◆ SDRAM_TIMING

#define SDRAM_TIMING   0x10C

Definition at line 168 of file dc21285reg.h.

◆ SDRAM_WINDOW_DISABLE

#define SDRAM_WINDOW_DISABLE   (1 << 31)

Definition at line 153 of file dc21285reg.h.

◆ TIMER_1_BASE

#define TIMER_1_BASE   0x300

Definition at line 355 of file dc21285reg.h.

◆ TIMER_1_CLEAR

#define TIMER_1_CLEAR   0x30C

Definition at line 379 of file dc21285reg.h.

◆ TIMER_1_CONTROL

#define TIMER_1_CONTROL   0x308

Definition at line 378 of file dc21285reg.h.

◆ TIMER_1_LOAD

#define TIMER_1_LOAD   0x300

Definition at line 376 of file dc21285reg.h.

◆ TIMER_1_VALUE

#define TIMER_1_VALUE   0x304

Definition at line 377 of file dc21285reg.h.

◆ TIMER_2_BASE

#define TIMER_2_BASE   0x320

Definition at line 356 of file dc21285reg.h.

◆ TIMER_2_CLEAR

#define TIMER_2_CLEAR   0x32C

Definition at line 383 of file dc21285reg.h.

◆ TIMER_2_CONTROL

#define TIMER_2_CONTROL   0x328

Definition at line 382 of file dc21285reg.h.

◆ TIMER_2_LOAD

#define TIMER_2_LOAD   0x320

Definition at line 380 of file dc21285reg.h.

◆ TIMER_2_VALUE

#define TIMER_2_VALUE   0x324

Definition at line 381 of file dc21285reg.h.

◆ TIMER_3_BASE

#define TIMER_3_BASE   0x340

Definition at line 357 of file dc21285reg.h.

◆ TIMER_3_CLEAR

#define TIMER_3_CLEAR   0x34C

Definition at line 387 of file dc21285reg.h.

◆ TIMER_3_CONTROL

#define TIMER_3_CONTROL   0x348

Definition at line 386 of file dc21285reg.h.

◆ TIMER_3_LOAD

#define TIMER_3_LOAD   0x340

Definition at line 384 of file dc21285reg.h.

◆ TIMER_3_VALUE

#define TIMER_3_VALUE   0x344

Definition at line 385 of file dc21285reg.h.

◆ TIMER_4_BASE

#define TIMER_4_BASE   0x360

Definition at line 358 of file dc21285reg.h.

◆ TIMER_4_CLEAR

#define TIMER_4_CLEAR   0x36C

Definition at line 391 of file dc21285reg.h.

◆ TIMER_4_CONTROL

#define TIMER_4_CONTROL   0x368

Definition at line 390 of file dc21285reg.h.

◆ TIMER_4_LOAD

#define TIMER_4_LOAD   0x360

Definition at line 388 of file dc21285reg.h.

◆ TIMER_4_VALUE

#define TIMER_4_VALUE   0x364

Definition at line 389 of file dc21285reg.h.

◆ TIMER_CLEAR

#define TIMER_CLEAR   0x0C

Definition at line 354 of file dc21285reg.h.

◆ TIMER_CONTROL

#define TIMER_CONTROL   0x08

Definition at line 353 of file dc21285reg.h.

◆ TIMER_ENABLE

#define TIMER_ENABLE   0x80

Definition at line 368 of file dc21285reg.h.

◆ TIMER_EXTERNAL

#define TIMER_EXTERNAL   0x0C

Definition at line 365 of file dc21285reg.h.

◆ TIMER_FCLK

#define TIMER_FCLK   0x00

Definition at line 362 of file dc21285reg.h.

◆ TIMER_FCLK_16

#define TIMER_FCLK_16   0x04

Definition at line 363 of file dc21285reg.h.

◆ TIMER_FCLK_256

#define TIMER_FCLK_256   0x08

Definition at line 364 of file dc21285reg.h.

◆ TIMER_LOAD

#define TIMER_LOAD   0x00

Definition at line 351 of file dc21285reg.h.

◆ TIMER_MAX_VAL

#define TIMER_MAX_VAL   0x00FFFFFF

Definition at line 372 of file dc21285reg.h.

◆ TIMER_MODE_FREERUN

#define TIMER_MODE_FREERUN   0x00

Definition at line 366 of file dc21285reg.h.

◆ TIMER_MODE_PERIODIC

#define TIMER_MODE_PERIODIC   0x40

Definition at line 367 of file dc21285reg.h.

◆ TIMER_VALUE

#define TIMER_VALUE   0x04

Definition at line 352 of file dc21285reg.h.

◆ UART_BRD

#define UART_BRD (   fclk,
 
)    (((fclk) / 4 / 16 / x) - 1)

Definition at line 285 of file dc21285reg.h.

◆ UART_BREAK

#define UART_BREAK   0x01

Definition at line 272 of file dc21285reg.h.

◆ UART_CONTROL

#define UART_CONTROL   0x174

Definition at line 287 of file dc21285reg.h.

◆ UART_DATA

#define UART_DATA   0x160

Definition at line 264 of file dc21285reg.h.

◆ UART_DATA_BITS_5

#define UART_DATA_BITS_5   0x00

Definition at line 279 of file dc21285reg.h.

◆ UART_DATA_BITS_6

#define UART_DATA_BITS_6   0x20

Definition at line 280 of file dc21285reg.h.

◆ UART_DATA_BITS_7

#define UART_DATA_BITS_7   0x40

Definition at line 281 of file dc21285reg.h.

◆ UART_DATA_BITS_8

#define UART_DATA_BITS_8   0x60

Definition at line 282 of file dc21285reg.h.

◆ UART_ENABLE

#define UART_ENABLE   0x01

Definition at line 288 of file dc21285reg.h.

◆ UART_ENABLE_FIFO

#define UART_ENABLE_FIFO   0x10

Definition at line 278 of file dc21285reg.h.

◆ UART_EVEN_PARITY

#define UART_EVEN_PARITY   0x04

Definition at line 275 of file dc21285reg.h.

◆ UART_FLAGS

#define UART_FLAGS   0x178

Definition at line 291 of file dc21285reg.h.

◆ UART_FRAME_ERROR

#define UART_FRAME_ERROR   0x02

Definition at line 267 of file dc21285reg.h.

◆ UART_H_UBRLCR

#define UART_H_UBRLCR   0x168

Definition at line 271 of file dc21285reg.h.

◆ UART_IRDA_ENABLE

#define UART_IRDA_ENABLE   0x04

Definition at line 290 of file dc21285reg.h.

◆ UART_L_UBRLCR

#define UART_L_UBRLCR   0x170

Definition at line 284 of file dc21285reg.h.

◆ UART_M_UBRLCR

#define UART_M_UBRLCR   0x16C

Definition at line 283 of file dc21285reg.h.

◆ UART_ODD_PARITY

#define UART_ODD_PARITY   0x00

Definition at line 274 of file dc21285reg.h.

◆ UART_OVERRUN_ERROR

#define UART_OVERRUN_ERROR   0x04

Definition at line 268 of file dc21285reg.h.

◆ UART_PARITY_ENABLE

#define UART_PARITY_ENABLE   0x02

Definition at line 273 of file dc21285reg.h.

◆ UART_PARITY_ERROR

#define UART_PARITY_ERROR   0x01

Definition at line 266 of file dc21285reg.h.

◆ UART_RX_ERROR

#define UART_RX_ERROR
Value:

Definition at line 269 of file dc21285reg.h.

◆ UART_RX_FULL

#define UART_RX_FULL   0x10

Definition at line 293 of file dc21285reg.h.

◆ UART_RX_STAT

#define UART_RX_STAT   0x164

Definition at line 265 of file dc21285reg.h.

◆ UART_SIR_ENABLE

#define UART_SIR_ENABLE   0x02

Definition at line 289 of file dc21285reg.h.

◆ UART_STOP_BITS_1

#define UART_STOP_BITS_1   0x00

Definition at line 276 of file dc21285reg.h.

◆ UART_STOP_BITS_2

#define UART_STOP_BITS_2   0x08

Definition at line 277 of file dc21285reg.h.

◆ UART_TX_BUSY

#define UART_TX_BUSY   0x08

Definition at line 292 of file dc21285reg.h.

◆ UART_TX_EMPTY

#define UART_TX_EMPTY   0x20

Definition at line 294 of file dc21285reg.h.

◆ VENDOR_ID

#define VENDOR_ID   0x00

Definition at line 48 of file dc21285reg.h.

◆ WATCHDOG_ENABLE

#define WATCHDOG_ENABLE   (1 << 13)

Definition at line 207 of file dc21285reg.h.

◆ XBUS_CYCLE_0_SHIFT

#define XBUS_CYCLE_0_SHIFT   0

Definition at line 231 of file dc21285reg.h.

◆ XBUS_CYCLE_1_SHIFT

#define XBUS_CYCLE_1_SHIFT   3

Definition at line 232 of file dc21285reg.h.

◆ XBUS_CYCLE_2_SHIFT

#define XBUS_CYCLE_2_SHIFT   6

Definition at line 233 of file dc21285reg.h.

◆ XBUS_CYCLE_3_SHIFT

#define XBUS_CYCLE_3_SHIFT   9

Definition at line 234 of file dc21285reg.h.

◆ XBUS_CYCLE_ARBITER

#define XBUS_CYCLE_ARBITER   0x148

Definition at line 230 of file dc21285reg.h.

◆ XBUS_CYCLE_STROBE_SHIFT

#define XBUS_CYCLE_STROBE_SHIFT   12

Definition at line 235 of file dc21285reg.h.

◆ XBUS_INT_IN_L0_HIGH

#define XBUS_INT_IN_L0_HIGH   (1 << 24)

Definition at line 238 of file dc21285reg.h.

◆ XBUS_INT_IN_L0_LOW

#define XBUS_INT_IN_L0_LOW   0

Definition at line 237 of file dc21285reg.h.

◆ XBUS_INT_IN_L1_HIGH

#define XBUS_INT_IN_L1_HIGH   (1 << 25)

Definition at line 240 of file dc21285reg.h.

◆ XBUS_INT_IN_L1_LOW

#define XBUS_INT_IN_L1_LOW   0

Definition at line 239 of file dc21285reg.h.

◆ XBUS_INT_IN_L2_HIGH

#define XBUS_INT_IN_L2_HIGH   (1 << 26)

Definition at line 242 of file dc21285reg.h.

◆ XBUS_INT_IN_L2_LOW

#define XBUS_INT_IN_L2_LOW   0

Definition at line 241 of file dc21285reg.h.

◆ XBUS_INT_IN_L3_HIGH

#define XBUS_INT_IN_L3_HIGH   (1 << 27)

Definition at line 244 of file dc21285reg.h.

◆ XBUS_INT_IN_L3_LOW

#define XBUS_INT_IN_L3_LOW   0

Definition at line 243 of file dc21285reg.h.

◆ XBUS_INT_XCS0_HIGH

#define XBUS_INT_XCS0_HIGH   (1 << 28)

Definition at line 246 of file dc21285reg.h.

◆ XBUS_INT_XCS0_LOW

#define XBUS_INT_XCS0_LOW   0

Definition at line 245 of file dc21285reg.h.

◆ XBUS_INT_XCS1_HIGH

#define XBUS_INT_XCS1_HIGH   (1 << 29)

Definition at line 248 of file dc21285reg.h.

◆ XBUS_INT_XCS1_LOW

#define XBUS_INT_XCS1_LOW   0

Definition at line 247 of file dc21285reg.h.

◆ XBUS_INT_XCS2_HIGH

#define XBUS_INT_XCS2_HIGH   (1 << 30)

Definition at line 250 of file dc21285reg.h.

◆ XBUS_INT_XCS2_LOW

#define XBUS_INT_XCS2_LOW   0

Definition at line 249 of file dc21285reg.h.

◆ XBUS_IO_STROBE_0_SHIFT

#define XBUS_IO_STROBE_0_SHIFT   0

Definition at line 254 of file dc21285reg.h.

◆ XBUS_IO_STROBE_2_SHIFT

#define XBUS_IO_STROBE_2_SHIFT   8

Definition at line 255 of file dc21285reg.h.

◆ XBUS_IO_STROBE_3_SHIFT

#define XBUS_IO_STROBE_3_SHIFT   16

Definition at line 256 of file dc21285reg.h.

◆ XBUS_IO_STROBE_4_SHIFT

#define XBUS_IO_STROBE_4_SHIFT   24

Definition at line 257 of file dc21285reg.h.

◆ XBUS_IO_STROBE_MASK

#define XBUS_IO_STROBE_MASK   0x14C

Definition at line 253 of file dc21285reg.h.

◆ XBUS_PCI_ARBITER

#define XBUS_PCI_ARBITER   (1 << 23)

Definition at line 236 of file dc21285reg.h.

◆ XBUS_PCI_INT_REQUEST

#define XBUS_PCI_INT_REQUEST   (1 << 31)

Definition at line 251 of file dc21285reg.h.

◆ XCS_DIRECTION_SHIFT

#define XCS_DIRECTION_SHIFT   28

Definition at line 222 of file dc21285reg.h.

UART_PARITY_ERROR
#define UART_PARITY_ERROR
Definition: dc21285reg.h:265
UART_FRAME_ERROR
#define UART_FRAME_ERROR
Definition: dc21285reg.h:266
UART_OVERRUN_ERROR
#define UART_OVERRUN_ERROR
Definition: dc21285reg.h:267

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