dev_footbridge.cc Source File
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55 #define DEV_FOOTBRIDGE_TICK_SHIFT 14
56 #define DEV_FOOTBRIDGE_LENGTH 0x400
58 #define N_FOOTBRIDGE_TIMERS 4
85 static void timer_tick0(
struct timer *
t,
void *
extra)
87 static void timer_tick1(
struct timer *
t,
void *extra)
89 static void timer_tick2(
struct timer *
t,
void *extra)
91 static void timer_tick3(
struct timer *
t,
void *extra)
105 freq /= (double)cycles;
112 if (d->
timer[timer_nr] == NULL) {
191 uint64_t idata = 0, odata = 0;
196 fatal(
"[ footbridge_isa: WARNING/TODO: write! ]\n");
224 debug(
"[ footbridge_reset: GP16: Halting. ]\n");
242 uint64_t idata = 0, odata = 0;
243 int bus, dev, func,
reg;
253 fatal(
"[ footbridge DEBUG ERROR: bus 255 unlikely,"
254 " pc (might not be updated) = 0x%08x ]\n", (
int)
cpu->
pc);
258 debug(
"[ footbridge pci: %s bus %i, device %i, function %i, register "
259 "%i ]\n", writeflag ==
MEM_READ?
"read from" :
"write to", bus,
263 &odata : &idata, len, writeflag);
275 uint64_t idata = 0, odata = 0;
283 relative_addr &= ~0x060;
286 switch (relative_addr) {
310 if (writeflag ==
MEM_WRITE && idata != 0)
311 fatal(
"[ footbridge: TODO: write to PCI_ADDRESS_"
312 "EXTENSION: 0x%llx ]\n", (
long long)idata);
338 fatal(
"[ WARNING: footbridge write to irq status? ]\n");
347 fatal(
"[ footbridge write to irq_raw_status ]\n");
361 fatal(
"[ WARNING: footbridge read from "
376 fatal(
"[ WARNING: footbridge read from "
377 "ENABLE CLEAR? ]\n");
386 fatal(
"[ WARNING: footbridge write to fiq status? ]\n");
395 fatal(
"[ footbridge write to fiq_raw_status ]\n");
415 reload_timer_value(
cpu, d, timer_nr);
437 fatal(
"TODO: footbridge timer: "
438 "both 16 and 256?\n");
442 reload_timer_value(
cpu, d, timer_nr);
452 reload_timer_value(
cpu, d, timer_nr);
464 fatal(
"[ footbridge read from sdram_ba_mask ]\n");
481 fatal(
"[ footbridge write to sdram_ba_mask "
482 "%#llx ]\n", (
long long)idata);
489 fatal(
"[ footbridge read from sdram_ba_offset ]\n");
493 fatal(
"[ footbridge write to sdram_ba_offset "
494 "%#llx ]\n", (
long long)idata);
498 default:
if (writeflag ==
MEM_READ) {
499 fatal(
"[ footbridge: read from 0x%x ]\n",
502 fatal(
"[ footbridge: write to 0x%x: 0x%llx ]\n",
503 (
int)relative_addr, (
long long)idata);
517 char irq_path[300], irq_path_isa[400];
518 uint64_t pci_addr = 0x7b000000;
534 0x79000000, 8, dev_footbridge_isa_access, d,
DM_DEFAULT, NULL);
540 snprintf(irq_path,
sizeof(irq_path),
"%s.footbridge",
542 for (i=0; i<32; i++) {
546 memset(&interrupt_template, 0,
sizeof(interrupt_template));
547 interrupt_template.
line = 1 << i;
548 snprintf(tmpstr,
sizeof(tmpstr),
"%s.%i", irq_path, i);
549 interrupt_template.
name = tmpstr;
551 interrupt_template.
extra = d;
565 snprintf(irq_path_isa,
sizeof(irq_path_isa),
"%s.10", irq_path);
568 snprintf(irq_path_isa,
sizeof(irq_path_isa),
"%s.11", irq_path);
570 default:
fatal(
"footbridge unimpl machine type\n");
603 "footbridge_reset", 0x7c000338, 1,
604 dev_footbridge_reset_access, d,
DM_DEFAULT, NULL);
606 default:
fatal(
"footbridge: unimplemented machine type.\n");
612 "footbridge_pci", pci_addr, 0x1000000,
613 dev_footbridge_pci_access, d,
DM_DEFAULT, NULL);
struct timer * timer_add(double freq, void(*timer_tick)(struct timer *timer, void *extra), void *extra)
void console_putchar(int handle, int ch)
#define INTERRUPT_CONNECT(name, istruct)
#define INTERRUPT_ASSERT(istruct)
void(* interrupt_deassert)(struct interrupt *)
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
#define PCI_ADDRESS_EXTENSION
struct pic8259_data * pic2
addr & if(addr >=0x24 &&page !=NULL)
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
struct pic8259_data * pic1
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
void fatal(const char *fmt,...)
struct isa_pic_data isa_pic_data
#define MACHINE_NETWINDER
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
#define TIMER_MODE_PERIODIC
int console_start_slave(struct machine *machine, const char *consolename, int use_for_input)
#define PCI_CENTRAL_FUNCTION
void timer_update_frequency(struct timer *t, double new_freq)
#define INTERRUPT_DEASSERT(istruct)
void(* interrupt_assert)(struct interrupt *)
void interrupt_handler_register(struct interrupt *templ)
#define MEM_PCI_LITTLE_ENDIAN
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
void bus_pci_add(struct machine *machine, struct pci_data *pci_data, struct memory *mem, int bus, int device, int function, const char *name)
#define CHECK_ALLOCATION(ptr)
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