cpu_arm.h Source File

Back to the index.

cpu_arm.h
Go to the documentation of this file.
1 #ifndef CPU_ARM_H
2 #define CPU_ARM_H
3 
4 /*
5  * Copyright (C) 2005-2019 Anders Gavare. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  * derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  *
31  * ARM CPU definitions.
32  */
33 
34 #include "misc.h"
35 #include "interrupt.h"
36 
37 struct cpu_family;
38 
39 /* ARM CPU types: */
41  const char *name;
42  uint32_t cpu_id;
43  int flags;
45  int iway;
47  int dway;
48 };
49 
50 
51 #define ARM_SL 10
52 #define ARM_FP 11
53 #define ARM_IP 12
54 #define ARM_SP 13
55 #define ARM_LR 14
56 #define ARM_PC 15
57 #define N_ARM_REGS 16
58 
59 #define ARM_REG_NAMES { \
60  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
61  "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }
62 
63 #define ARM_CONDITION_STRINGS { \
64  "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \
65  "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }
66 
67 /* Names of Data Processing Instructions: */
68 #define ARM_DPI_NAMES { \
69  "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70  "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71 
72 #define ARM_THUMB_DPI_NAMES { \
73  "ands", "eors", "lsls", "lsrs", "asrs", "adcs", "sbcs", "rors", \
74  "tst", "negs", "cmp", "cmn", "orrs", "muls", "bics", "mvns" }
75 
76 #define ARM_IC_ENTRIES_SHIFT 10
77 
78 #define ARM_N_IC_ARGS 3
79 #define ARM_INSTR_ALIGNMENT_SHIFT 2
80 #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT)
81 #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
82  & (ARM_IC_ENTRIES_PER_PAGE-1))
83 #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \
84  + ARM_INSTR_ALIGNMENT_SHIFT))
85 
86 #define ARM_F_N 8 /* Same as ARM_FLAG_*, but */
87 #define ARM_F_Z 4 /* for the 'flags' field instead */
88 #define ARM_F_C 2 /* of cpsr. */
89 #define ARM_F_V 1
90 
91 #define ARM_FLAG_N 0x80000000 /* Negative flag */
92 #define ARM_FLAG_Z 0x40000000 /* Zero flag */
93 #define ARM_FLAG_C 0x20000000 /* Carry flag */
94 #define ARM_FLAG_V 0x10000000 /* Overflow flag */
95 #define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */
96 #define ARM_FLAG_J 0x01000000 /* Java flag (BXJ instruction ARMv5J) */
97 #define ARM_FLAG_E 0x00000200 /* Data Endianness (SETEND instruction ARMv6) */
98 #define ARM_FLAG_A 0x00000100 /* A = 1 disables Imprecise Data Aborts (ARMv6) */
99 #define ARM_FLAG_I 0x00000080 /* Interrupt disable */
100 #define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */
101 #define ARM_FLAG_T 0x00000020 /* Thumb mode */
102 
103 #define ARM_FLAG_MODE 0x0000001f
104 #define ARM_MODE_USR26 0x00
105 #define ARM_MODE_FIQ26 0x01
106 #define ARM_MODE_IRQ26 0x02
107 #define ARM_MODE_SVC26 0x03
108 #define ARM_MODE_USR32 0x10
109 #define ARM_MODE_FIQ32 0x11
110 #define ARM_MODE_IRQ32 0x12
111 #define ARM_MODE_SVC32 0x13
112 #define ARM_MODE_ABT32 0x17
113 #define ARM_MODE_UND32 0x1b
114 #define ARM_MODE_SYS32 0x1f
115 
116 #define ARM_EXCEPTION_TO_MODE { \
117  ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
118  ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 }
119 
120 #define N_ARM_EXCEPTIONS 8
121 
122 #define ARM_EXCEPTION_RESET 0
123 #define ARM_EXCEPTION_UND 1
124 #define ARM_EXCEPTION_SWI 2
125 #define ARM_EXCEPTION_PREF_ABT 3
126 #define ARM_EXCEPTION_DATA_ABT 4
127 /* 5 was address exception in 26-bit ARM */
128 #define ARM_EXCEPTION_IRQ 6
129 #define ARM_EXCEPTION_FIQ 7
130 
131 DYNTRANS_MISC_DECLARATIONS(arm,ARM,uint32_t)
132 
133 #define ARM_MAX_VPH_TLB_ENTRIES 384
134 
135 
136 struct arm_cpu {
137  /*
138  * Misc.:
139  */
140  struct arm_cpu_type_def cpu_type;
141  uint32_t of_emul_addr;
142 
143  void (*coproc[16])(struct cpu *, int opcode1,
144  int opcode2, int l_bit, int crn, int crm,
145  int rd);
146 
147  /*
148  * General Purpose Registers (including the program counter):
149  *
150  * r[] always contains the current register set. The others are
151  * only used to swap to/from when changing modes. (An exception is
152  * r[0..7], which are never swapped out, they are always present.)
153  */
154 
155  uint32_t r[N_ARM_REGS];
156 
157  uint32_t default_r8_r14[7]; /* usr and sys */
158  uint32_t fiq_r8_r14[7];
159  uint32_t irq_r13_r14[2];
160  uint32_t svc_r13_r14[2];
161  uint32_t abt_r13_r14[2];
162  uint32_t und_r13_r14[2];
163 
164  uint32_t tmp_pc; /* Used for load/stores */
165  uint32_t tmp_branch; /* Set by THUMB branch prefix instruction */
166 
167  /*
168  * Flag/status registers:
169  *
170  * NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
171  * the flags should be copied from 'flags', and when cpsr is written
172  * to, 'flags' should be updated as well.
173  */
174  size_t flags;
175  uint32_t cpsr;
176  uint32_t spsr_svc;
177  uint32_t spsr_abt;
178  uint32_t spsr_und;
179  uint32_t spsr_irq;
180  uint32_t spsr_fiq;
181 
182 
183  /*
184  * System Control Coprocessor registers:
185  */
186  uint32_t cachetype; /* Cache Type Register */
187  uint32_t control; /* Control Register */
188  uint32_t auxctrl; /* Aux. Control Register */
189  uint32_t ttb; /* Translation Table Base */
190  uint32_t dacr; /* Domain Access Control */
191  uint32_t fsr; /* Fault Status Register */
192  uint32_t far; /* Fault Address Register */
193  uint32_t pid; /* Process Id Register */
194  uint32_t cpar; /* CoProcessor Access Reg. */
195 
196  /* i80321 Coprocessor 6: ICU (Interrupt controller) */
197  uint32_t i80321_inten; /* enable */
198  uint32_t i80321_isteer;
199  uint32_t i80321_isrc; /* current assertions */
200  uint32_t tmr0;
201  uint32_t tmr1;
202  struct interrupt tmr0_irq;
203  struct interrupt tmr1_irq;
204  uint32_t tcr0;
205  uint32_t tcr1;
206  uint32_t trr0;
207  uint32_t trr1;
208  uint32_t tisr;
209  uint32_t wdtcr;
210 
211  /* XScale Coprocessor 14: (Performance Monitoring Unit) */
212  /* XSC1 access style: */
213  uint32_t xsc1_pmnc; /* Perf. Monitor Ctrl Reg. */
214  uint32_t xsc1_ccnt; /* Clock Counter */
215  uint32_t xsc1_pmn0; /* Perf. Counter Reg. 0 */
216  uint32_t xsc1_pmn1; /* Perf. Counter Reg. 1 */
217  /* XSC2 access style: */
218  uint32_t xsc2_pmnc; /* Perf. Monitor Ctrl Reg. */
219  uint32_t xsc2_ccnt; /* Clock Counter */
220  uint32_t xsc2_inten; /* Interrupt Enable */
221  uint32_t xsc2_flag; /* Overflow Flag Register */
222  uint32_t xsc2_evtsel; /* Event Selection Register */
223  uint32_t xsc2_pmn0; /* Perf. Counter Reg. 0 */
224  uint32_t xsc2_pmn1; /* Perf. Counter Reg. 1 */
225  uint32_t xsc2_pmn2; /* Perf. Counter Reg. 2 */
226  uint32_t xsc2_pmn3; /* Perf. Counter Reg. 3 */
227 
228  /* For caching the host address of the L1 translation table: */
229  unsigned char *translation_table;
230  uint32_t last_ttb;
231 
232  /*
233  * Interrupts:
234  */
236 
237  /* Read-Modify-Write (LDREX/STREX): */
238  int rmw; /* 1 = currently active */
239  uint32_t rmw_len; /* Length of rmw modification */
240  uint32_t rmw_addr; /* Address of rmw modification */
241 
242 
243  /*
244  * Instruction translation cache, and 32-bit virtual -> physical ->
245  * host address translation:
246  */
247  DYNTRANS_ITC(arm)
248  VPH_TLBS(arm,ARM)
249  VPH32_16BITVPHENTRIES(arm,ARM)
250 
251  /* ARM specific: */
253 };
254 
255 
256 /* System Control Coprocessor, control bits: */
257 #define ARM_CONTROL_MMU 0x0001
258 #define ARM_CONTROL_ALIGN 0x0002
259 #define ARM_CONTROL_CACHE 0x0004
260 #define ARM_CONTROL_WBUFFER 0x0008
261 #define ARM_CONTROL_PROG32 0x0010
262 #define ARM_CONTROL_DATA32 0x0020
263 #define ARM_CONTROL_BIG 0x0080
264 #define ARM_CONTROL_S 0x0100
265 #define ARM_CONTROL_R 0x0200
266 #define ARM_CONTROL_F 0x0400
267 #define ARM_CONTROL_Z 0x0800
268 #define ARM_CONTROL_ICACHE 0x1000
269 #define ARM_CONTROL_V 0x2000
270 #define ARM_CONTROL_RR 0x4000
271 #define ARM_CONTROL_L4 0x8000
272 
273 /* Auxiliary Control Register bits: */
274 #define ARM_AUXCTRL_MD 0x30 /* MiniData Cache Attribute */
275 #define ARM_AUXCTRL_MD_SHIFT 4
276 #define ARM_AUXCTRL_P 0x02 /* Page Table Memory Attribute */
277 #define ARM_AUXCTRL_K 0x01 /* Write Buffer Coalescing Disable */
278 
279 /* Cache Type register bits: */
280 #define ARM_CACHETYPE_CLASS 0x1e000000
281 #define ARM_CACHETYPE_CLASS_SHIFT 25
282 #define ARM_CACHETYPE_HARVARD 0x01000000
283 #define ARM_CACHETYPE_HARVARD_SHIFT 24
284 #define ARM_CACHETYPE_DSIZE 0x001c0000
285 #define ARM_CACHETYPE_DSIZE_SHIFT 18
286 #define ARM_CACHETYPE_DASSOC 0x00038000
287 #define ARM_CACHETYPE_DASSOC_SHIFT 15
288 #define ARM_CACHETYPE_DLINE 0x00003000
289 #define ARM_CACHETYPE_DLINE_SHIFT 12
290 #define ARM_CACHETYPE_ISIZE 0x000001c0
291 #define ARM_CACHETYPE_ISIZE_SHIFT 6
292 #define ARM_CACHETYPE_IASSOC 0x00000038
293 #define ARM_CACHETYPE_IASSOC_SHIFT 3
294 #define ARM_CACHETYPE_ILINE 0x00000003
295 #define ARM_CACHETYPE_ILINE_SHIFT 0
296 
297 /* cpu_arm.c: */
298 void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
299 void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
300  uint32_t paddr);
301 void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
302  uint32_t paddr);
303 void arm_exception(struct cpu *, int);
304 int arm_cpu_interpret_thumb_SLOW(struct cpu*);
305 int arm_run_instr(struct cpu *cpu);
306 void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
307  unsigned char *host_page, int writeflag, uint64_t paddr_page);
308 void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
309 void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
310 void arm_load_register_bank(struct cpu *cpu);
311 void arm_save_register_bank(struct cpu *cpu);
312 int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
313  unsigned char *data, size_t len, int writeflag, int cache_flags);
315 
316 /* cpu_arm_coproc.c: */
317 void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
318  int crn, int crm, int rd);
319 void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
320  int crn, int crm, int rd);
321 void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
322  int crn, int crm, int rd);
323 
324 /* cpu_arm_instr.c: */
325 void arm_push(struct cpu* cpu, uint32_t* np, int p_bit, int u_bit, int s_bit, int w_bit, uint16_t regs);
326 void arm_pop(struct cpu* cpu, uint32_t* np, int p_bit, int u_bit, int s_bit, int w_bit, uint32_t iw);
327 
328 /* memory_arm.c: */
329 int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr,
330  uint64_t *return_addr, int flags);
331 int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr,
332  uint64_t *return_addr, int flags);
333 
334 #endif /* CPU_ARM_H */
arm_exception
void arm_exception(struct cpu *, int)
Definition: cpu_arm.cc:608
arm_cpu::i80321_isrc
uint32_t i80321_isrc
Definition: cpu_arm.h:199
N_VPH32_ENTRIES
#define N_VPH32_ENTRIES
Definition: cpu.h:188
arm_cpu::xsc2_evtsel
uint32_t xsc2_evtsel
Definition: cpu_arm.h:222
data
u_short data
Definition: siireg.h:79
arm_cpu_family_init
int arm_cpu_family_init(struct cpu_family *)
arm_coproc_i80321_6
void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
Definition: cpu_arm_coproc.cc:292
arm_cpu_interpret_thumb_SLOW
int arm_cpu_interpret_thumb_SLOW(struct cpu *)
Definition: cpu_arm.cc:1097
arm_cpu::tcr1
uint32_t tcr1
Definition: cpu_arm.h:205
arm_cpu::tmr1_irq
struct interrupt tmr1_irq
Definition: cpu_arm.h:203
arm_cpu_type_def::iway
int iway
Definition: cpu_arm.h:45
memory
Definition: memory.h:75
arm_cpu::tmp_pc
uint32_t tmp_pc
Definition: cpu_arm.h:164
arm_push
void arm_push(struct cpu *cpu, uint32_t *np, int p_bit, int u_bit, int s_bit, int w_bit, uint16_t regs)
Definition: cpu_arm_instr.cc:1518
arm_cpu::xsc2_ccnt
uint32_t xsc2_ccnt
Definition: cpu_arm.h:219
VPH32_16BITVPHENTRIES
#define VPH32_16BITVPHENTRIES(arch, ARCH)
Definition: cpu.h:195
arm_cpu
Definition: cpu_arm.h:136
arm_cpu::default_r8_r14
uint32_t default_r8_r14[7]
Definition: cpu_arm.h:157
arm_cpu::auxctrl
uint32_t auxctrl
Definition: cpu_arm.h:188
arm_cpu::coproc
void(* coproc[16])(struct cpu *, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
Definition: cpu_arm.h:143
arm_translate_v2p_mmu
int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
Definition: memory_arm.cc:114
N_ARM_REGS
#define N_ARM_REGS
Definition: cpu_arm.h:57
arm_cpu::tcr0
uint32_t tcr0
Definition: cpu_arm.h:204
arm_cpu::dacr
uint32_t dacr
Definition: cpu_arm.h:190
arm_cpu::of_emul_addr
uint32_t of_emul_addr
Definition: cpu_arm.h:141
arm_translation_table_set_l1
void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, uint32_t paddr)
Definition: cpu_arm.cc:256
arm_cpu::cpsr
uint32_t cpsr
Definition: cpu_arm.h:175
arm_translation_table_set_l1_b
void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr, uint32_t paddr)
Definition: cpu_arm.cc:284
DYNTRANS_MISC_DECLARATIONS
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
Definition: cpu.h:72
arm_cpu::tmr0
uint32_t tmr0
Definition: cpu_arm.h:200
arm_cpu::far
uint32_t far
Definition: cpu_arm.h:192
arm_cpu::xsc2_pmnc
uint32_t xsc2_pmnc
Definition: cpu_arm.h:218
arm_cpu::control
uint32_t control
Definition: cpu_arm.h:187
arm_cpu::xsc2_pmn1
uint32_t xsc2_pmn1
Definition: cpu_arm.h:224
arm_save_register_bank
void arm_save_register_bank(struct cpu *cpu)
Definition: cpu_arm.cc:514
arm_cpu::xsc2_pmn2
uint32_t xsc2_pmn2
Definition: cpu_arm.h:225
arm_cpu::translation_table
unsigned char * translation_table
Definition: cpu_arm.h:229
arm_cpu::fsr
uint32_t fsr
Definition: cpu_arm.h:191
arm_load_register_bank
void arm_load_register_bank(struct cpu *cpu)
Definition: cpu_arm.cc:561
DYNTRANS_ITC
#define DYNTRANS_ITC(arch)
Definition: cpu.h:143
arm_cpu::flags
size_t flags
Definition: cpu_arm.h:174
arm_cpu::tmp_branch
uint32_t tmp_branch
Definition: cpu_arm.h:165
arm_cpu::xsc2_pmn3
uint32_t xsc2_pmn3
Definition: cpu_arm.h:226
arm_cpu::spsr_und
uint32_t spsr_und
Definition: cpu_arm.h:178
interrupt.h
arm_cpu::rmw_len
uint32_t rmw_len
Definition: cpu_arm.h:239
arm_cpu::und_r13_r14
uint32_t und_r13_r14[2]
Definition: cpu_arm.h:162
arm_cpu::spsr_irq
uint32_t spsr_irq
Definition: cpu_arm.h:179
arm_cpu::tisr
uint32_t tisr
Definition: cpu_arm.h:208
arm_cpu::rmw
int rmw
Definition: cpu_arm.h:238
misc.h
arm_cpu::tmr0_irq
struct interrupt tmr0_irq
Definition: cpu_arm.h:202
arm_cpu::cachetype
uint32_t cachetype
Definition: cpu_arm.h:186
arm_cpu::irq_asserted
int irq_asserted
Definition: cpu_arm.h:235
VPH_TLBS
#define VPH_TLBS(arch, ARCH)
Definition: cpu.h:157
arm_cpu::xsc2_flag
uint32_t xsc2_flag
Definition: cpu_arm.h:221
arm_cpu::cpar
uint32_t cpar
Definition: cpu_arm.h:194
arm_cpu::tmr1
uint32_t tmr1
Definition: cpu_arm.h:201
arm_cpu::spsr_abt
uint32_t spsr_abt
Definition: cpu_arm.h:177
arm_translate_v2p
int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
Definition: memory_arm.cc:54
arm_cpu::r
uint32_t r[N_ARM_REGS]
Definition: cpu_arm.h:155
arm_cpu::i80321_inten
uint32_t i80321_inten
Definition: cpu_arm.h:197
arm_cpu_type_def::name
const char * name
Definition: cpu_arm.h:41
arm_invalidate_code_translation
void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
arm_run_instr
int arm_run_instr(struct cpu *cpu)
arm_cpu_type_def::flags
int flags
Definition: cpu_arm.h:43
arm_cpu::xsc2_inten
uint32_t xsc2_inten
Definition: cpu_arm.h:220
arm_cpu::trr0
uint32_t trr0
Definition: cpu_arm.h:206
arm_cpu::spsr_fiq
uint32_t spsr_fiq
Definition: cpu_arm.h:180
arm_cpu_type_def
Definition: cpu_arm.h:40
arm_cpu::rmw_addr
uint32_t rmw_addr
Definition: cpu_arm.h:240
arm_cpu_type_def::cpu_id
uint32_t cpu_id
Definition: cpu_arm.h:42
arm_cpu::last_ttb
uint32_t last_ttb
Definition: cpu_arm.h:230
arm_update_translation_table
void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
arm_cpu_type_def::dway
int dway
Definition: cpu_arm.h:47
arm_cpu::i80321_isteer
uint32_t i80321_isteer
Definition: cpu_arm.h:198
arm_cpu::irq_r13_r14
uint32_t irq_r13_r14[2]
Definition: cpu_arm.h:159
arm_cpu_type_def::icache_shift
int icache_shift
Definition: cpu_arm.h:44
arm_cpu::ttb
uint32_t ttb
Definition: cpu_arm.h:189
arm_cpu::cpu_type
struct arm_cpu_type_def cpu_type
Definition: cpu_arm.h:140
arm_cpu::xsc1_pmn0
uint32_t xsc1_pmn0
Definition: cpu_arm.h:215
arm_cpu::wdtcr
uint32_t wdtcr
Definition: cpu_arm.h:209
arm_cpu::trr1
uint32_t trr1
Definition: cpu_arm.h:207
arm_cpu::xsc1_pmnc
uint32_t xsc1_pmnc
Definition: cpu_arm.h:213
arm_invalidate_translation_caches
void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
arm_cpu_type_def::dcache_shift
int dcache_shift
Definition: cpu_arm.h:46
arm_setup_initial_translation_table
void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr)
Definition: cpu_arm.cc:220
arm_cpu::abt_r13_r14
uint32_t abt_r13_r14[2]
Definition: cpu_arm.h:161
interrupt
Definition: interrupt.h:36
arm_cpu::pid
uint32_t pid
Definition: cpu_arm.h:193
arm_pop
void arm_pop(struct cpu *cpu, uint32_t *np, int p_bit, int u_bit, int s_bit, int w_bit, uint32_t iw)
Definition: cpu_arm_instr.cc:1352
arm_memory_rw
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
arm_cpu::svc_r13_r14
uint32_t svc_r13_r14[2]
Definition: cpu_arm.h:160
arm_cpu::xsc2_pmn0
uint32_t xsc2_pmn0
Definition: cpu_arm.h:223
cpu
Definition: cpu.h:326
arm_cpu::spsr_svc
uint32_t spsr_svc
Definition: cpu_arm.h:176
arm_cpu::xsc1_pmn1
uint32_t xsc1_pmn1
Definition: cpu_arm.h:216
arm_cpu::is_userpage
uint32_t is_userpage[N_VPH32_ENTRIES/32]
Definition: cpu_arm.h:252
arm_coproc_xscale_14
void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
Definition: cpu_arm_coproc.cc:416
arm_cpu::xsc1_ccnt
uint32_t xsc1_ccnt
Definition: cpu_arm.h:214
cpu_family
Definition: cpu.h:256
arm_coproc_15
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
Definition: cpu_arm_coproc.cc:50
arm_cpu::fiq_r8_r14
uint32_t fiq_r8_r14[7]
Definition: cpu_arm.h:158

Generated on Tue Aug 25 2020 19:25:06 for GXemul by doxygen 1.8.18