RAMComponent.cc Source File

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RAMComponent.cc
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1 /*
2  * Copyright (C) 2008-2019 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <iomanip>
29 #include <assert.h>
30 #include <sys/mman.h>
31 
33 #include "GXemul.h"
34 
35 
36 RAMComponent::RAMComponent(const string& visibleClassName)
37  : MemoryMappedComponent("ram", visibleClassName)
38  , m_blockSizeShift(22) // 22 = 4 MB per block
39  , m_blockSize(1 << m_blockSizeShift)
40  , m_dataHandler(*this)
41  , m_writeProtected(false)
42  , m_lastDumpAddr(0)
43  , m_addressSelect(0)
44  , m_selectedHostMemoryBlock(NULL)
45  , m_selectedOffsetWithinBlock(0)
46 {
47  AddVariable("writeProtect", &m_writeProtected);
48  AddVariable("lastDumpAddr", &m_lastDumpAddr);
49  AddCustomVariable("data", &m_dataHandler);
50 }
51 
52 
54 {
55  ReleaseAllBlocks();
56 }
57 
58 
59 void RAMComponent::ReleaseAllBlocks()
60 {
61  for (size_t i=0; i<m_memoryBlocks.size(); ++i) {
62  if (m_memoryBlocks[i] != NULL) {
63  munmap(m_memoryBlocks[i], m_blockSize);
64  m_memoryBlocks[i] = NULL;
65  }
66  }
67 }
68 
69 
71 {
72  return new RAMComponent();
73 }
74 
75 
76 string RAMComponent::GetAttribute(const string& attributeName)
77 {
78  if (attributeName == "description")
79  return "A generic RAM component.";
80 
81  return MemoryMappedComponent::GetAttribute(attributeName);
82 }
83 
84 
86 {
87  ReleaseAllBlocks();
88 }
89 
90 
91 void RAMComponent::GetMethodNames(vector<string>& names) const
92 {
93  // Add our method names...
94  names.push_back("dump");
95 
96  // ... and make sure to call the base class implementation:
98 }
99 
100 
101 bool RAMComponent::MethodMayBeReexecutedWithoutArgs(const string& methodName) const
102 {
103  if (methodName == "dump")
104  return true;
105 
106  // ... and make sure to call the base class implementation:
108 }
109 
110 
111 void RAMComponent::ExecuteMethod(GXemul* gxemul, const string& methodName,
112  const vector<string>& arguments)
113 {
114  if (methodName == "dump") {
115  uint64_t vaddr = m_lastDumpAddr;
116 
117  if (arguments.size() > 1) {
118  gxemul->GetUI()->ShowDebugMessage("syntax: .dump [addr]\n");
119  return;
120  }
121 
122  if (arguments.size() == 1) {
123  gxemul->GetUI()->ShowDebugMessage("TODO: parse address expression\n");
124  gxemul->GetUI()->ShowDebugMessage("(for now, only hex immediate values are supported!)\n");
125 
126  stringstream ss;
127  ss << arguments[0];
128  ss.flags(std::ios::hex);
129  ss >> vaddr;
130  }
131 
132  const int nRows = 16;
133  for (int i=0; i<nRows; i++) {
134  const size_t len = 16;
135  unsigned char data[len];
136  bool readable[len];
137 
138  stringstream ss;
139  ss.flags(std::ios::hex);
140 
141  if (vaddr > 0xffffffff)
142  ss << std::setw(16);
143  else
144  ss << std::setw(8);
145 
146  ss << std::setfill('0') << vaddr;
147 
148  size_t k;
149  for (k=0; k<len; ++k) {
150  AddressSelect(vaddr + k);
151  readable[k] = ReadData(data[k], BigEndian);
152  }
153 
154  ss << " ";
155 
156  for (k=0; k<len; ++k) {
157  if ((k&3) == 0)
158  ss << " ";
159 
160  ss << std::setw(2) << std::setfill('0');
161  if (readable[k])
162  ss << (int)data[k];
163  else
164  ss << "--";
165  }
166 
167  ss << " ";
168 
169  for (k=0; k<len; ++k) {
170  char s[2];
171  s[0] = data[k] >= 32 && data[k] < 127? data[k] : '.';
172  s[1] = '\0';
173 
174  if (readable[k])
175  ss << s;
176  else
177  ss << "-";
178  }
179 
180  ss << "\n";
181 
182  gxemul->GetUI()->ShowDebugMessage(ss.str());
183 
184  vaddr += len;
185  }
186 
187  m_lastDumpAddr = vaddr;
188 
189  return;
190  }
191 
192  // Call base...
193  Component::ExecuteMethod(gxemul, methodName, arguments);
194 }
195 
196 
198 {
199  return this;
200 }
201 
202 
203 void RAMComponent::AddressSelect(uint64_t address)
204 {
205  m_addressSelect = address;
206 
207  uint64_t blockNr = address >> m_blockSizeShift;
208 
209  if (blockNr+1 > m_memoryBlocks.size())
210  m_selectedHostMemoryBlock = NULL;
211  else
212  m_selectedHostMemoryBlock = m_memoryBlocks[blockNr];
213 
214  m_selectedOffsetWithinBlock = address & (m_blockSize-1);
215 }
216 
217 
218 void* RAMComponent::AllocateBlock()
219 {
220  void * p = mmap(NULL, m_blockSize, PROT_WRITE | PROT_READ,
221  MAP_ANON | MAP_PRIVATE, -1, 0);
222 
223  if (p == MAP_FAILED || p == NULL) {
224  std::cerr << "RAMComponent::AllocateBlock: Could not allocate "
225  << m_blockSize << " bytes. Aborting.\n";
226  throw std::exception();
227  }
228 
229  uint64_t blockNr = m_addressSelect >> m_blockSizeShift;
230 
231  if (blockNr+1 > m_memoryBlocks.size())
232  m_memoryBlocks.resize(blockNr + 1);
233 
234  m_memoryBlocks[blockNr] = p;
235 
236  return p;
237 }
238 
239 
240 bool RAMComponent::ReadData(uint8_t& data, Endianness endianness)
241 {
242  if (m_selectedHostMemoryBlock == NULL)
243  data = 0;
244  else
245  data = (((uint8_t*)m_selectedHostMemoryBlock)
246  [m_selectedOffsetWithinBlock]);
247 
248  return true;
249 }
250 
251 
252 bool RAMComponent::ReadData(uint16_t& data, Endianness endianness)
253 {
254  assert((m_addressSelect & 1) == 0);
255 
256  if (m_selectedHostMemoryBlock == NULL)
257  data = 0;
258  else
259  data = (((uint16_t*)m_selectedHostMemoryBlock)
260  [m_selectedOffsetWithinBlock >> 1]);
261 
262  if (endianness == BigEndian)
264  else
266 
267  return true;
268 }
269 
270 
271 bool RAMComponent::ReadData(uint32_t& data, Endianness endianness)
272 {
273  assert((m_addressSelect & 3) == 0);
274 
275  if (m_selectedHostMemoryBlock == NULL)
276  data = 0;
277  else
278  data = (((uint32_t*)m_selectedHostMemoryBlock)
279  [m_selectedOffsetWithinBlock >> 2]);
280 
281  if (endianness == BigEndian)
283  else
285 
286  return true;
287 }
288 
289 
290 bool RAMComponent::ReadData(uint64_t& data, Endianness endianness)
291 {
292  assert((m_addressSelect & 7) == 0);
293 
294  if (m_selectedHostMemoryBlock == NULL)
295  data = 0;
296  else
297  data = (((uint64_t*)m_selectedHostMemoryBlock)
298  [m_selectedOffsetWithinBlock >> 3]);
299 
300  if (endianness == BigEndian)
302  else
304 
305  return true;
306 }
307 
308 
309 bool RAMComponent::WriteData(const uint8_t& data, Endianness endianness)
310 {
311  if (m_writeProtected)
312  return false;
313 
314  if (m_selectedHostMemoryBlock == NULL)
315  m_selectedHostMemoryBlock = AllocateBlock();
316 
317  (((uint8_t*)m_selectedHostMemoryBlock)
318  [m_selectedOffsetWithinBlock]) = data;
319 
320  return true;
321 }
322 
323 
324 bool RAMComponent::WriteData(const uint16_t& data, Endianness endianness)
325 {
326  assert((m_addressSelect & 1) == 0);
327 
328  if (m_writeProtected)
329  return false;
330 
331  if (m_selectedHostMemoryBlock == NULL)
332  m_selectedHostMemoryBlock = AllocateBlock();
333 
334  uint16_t d;
335  if (endianness == BigEndian)
336  d = BE16_TO_HOST(data);
337  else
338  d = LE16_TO_HOST(data);
339 
340  (((uint16_t*)m_selectedHostMemoryBlock)
341  [m_selectedOffsetWithinBlock >> 1]) = d;
342 
343  return true;
344 }
345 
346 
347 bool RAMComponent::WriteData(const uint32_t& data, Endianness endianness)
348 {
349  assert((m_addressSelect & 3) == 0);
350 
351  if (m_writeProtected)
352  return false;
353 
354  if (m_selectedHostMemoryBlock == NULL)
355  m_selectedHostMemoryBlock = AllocateBlock();
356 
357  uint32_t d;
358  if (endianness == BigEndian)
359  d = BE32_TO_HOST(data);
360  else
361  d = LE32_TO_HOST(data);
362 
363  (((uint32_t*)m_selectedHostMemoryBlock)
364  [m_selectedOffsetWithinBlock >> 2]) = d;
365 
366  return true;
367 }
368 
369 
370 bool RAMComponent::WriteData(const uint64_t& data, Endianness endianness)
371 {
372  assert((m_addressSelect & 7) == 0);
373 
374  if (m_writeProtected)
375  return false;
376 
377  if (m_selectedHostMemoryBlock == NULL)
378  m_selectedHostMemoryBlock = AllocateBlock();
379 
380  uint64_t d;
381  if (endianness == BigEndian)
382  d = BE64_TO_HOST(data);
383  else
384  d = LE64_TO_HOST(data);
385 
386  (((uint64_t*)m_selectedHostMemoryBlock)
387  [m_selectedOffsetWithinBlock >> 3]) = d;
388 
389  return true;
390 }
391 
392 
393 /*****************************************************************************/
394 
395 
396 #ifdef WITHUNITTESTS
397 
398 #include "ComponentFactory.h"
399 
400 static void Test_RAMComponent_AddressDataBus()
401 {
403 
404  AddressDataBus* bus = ram->AsAddressDataBus();
405  UnitTest::Assert("The RAMComponent should implement the "
406  "AddressDataBus interface", bus != NULL);
407 }
408 
409 static void Test_RAMComponent_InitiallyZero()
410 {
412  AddressDataBus* bus = ram->AsAddressDataBus();
413 
414  bus->AddressSelect(0);
415 
416  // By default, RAM should be zero-filled:
417  uint8_t data8 = 42;
418  bus->ReadData(data8);
419  UnitTest::Assert("A: memory should be zero filled (8)", data8, 0);
420 
421  uint16_t data16 = 142;
422  bus->ReadData(data16, BigEndian);
423  UnitTest::Assert("A: memory should be zero filled (16)", data16, 0);
424 
425  uint32_t data32 = 342;
426  bus->ReadData(data32, BigEndian);
427  UnitTest::Assert("A: memory should be zero filled (32)", data32, 0);
428 
429  uint64_t data64 = 942;
430  bus->ReadData(data64, BigEndian);
431  UnitTest::Assert("A: memory should be zero filled (64)", data64, 0);
432 
433  bus->AddressSelect(0x10000);
434 
435  data8 = 43;
436  bus->ReadData(data8);
437  UnitTest::Assert("B: memory should be zero filled (8)", data8, 0);
438 
439  data16 = 143;
440  bus->ReadData(data16, BigEndian);
441  UnitTest::Assert("B: memory should be zero filled (16)", data16, 0);
442 
443  data32 = 343;
444  bus->ReadData(data32, BigEndian);
445  UnitTest::Assert("B: memory should be zero filled (32)", data32, 0);
446 
447  data64 = 943;
448  bus->ReadData(data64, BigEndian);
449  UnitTest::Assert("B: memory should be zero filled (64)", data64, 0);
450 }
451 
452 static void Test_RAMComponent_WriteThenRead()
453 {
455  AddressDataBus* bus = ram->AsAddressDataBus();
456 
457  bus->AddressSelect(256);
458 
459  uint64_t data64 = ((uint64_t)0x1234567 << 32) | 0x89abcdef;
460  bus->WriteData(data64, BigEndian);
461 
462  uint64_t data64_b = 0;
463  bus->ReadData(data64_b, BigEndian);
464 
465  UnitTest::Assert("memory should be same when read", data64_b, data64);
466 
467  uint32_t data32_b = 0;
468  bus->ReadData(data32_b, BigEndian);
469 
470  UnitTest::Assert("32-bit read should give top 32 bits, "
471  "in big endian mode", data32_b, data64 >> 32);
472 
473  uint16_t data16_b = 0;
474  bus->ReadData(data16_b, BigEndian);
475 
476  UnitTest::Assert("16-bit read should give top 16 bits, "
477  "in big endian mode", data16_b, data64 >> 48);
478 
479  uint8_t data8_b = 0;
480  bus->ReadData(data8_b);
481 
482  UnitTest::Assert("8-bit read should give top 8 bits, "
483  "in big endian mode", data8_b, data64 >> 56);
484 }
485 
486 static void Test_RAMComponent_WriteThenRead_ReverseEndianness()
487 {
489  AddressDataBus* bus = ram->AsAddressDataBus();
490 
491  bus->AddressSelect(256);
492 
493  uint64_t data64 = ((uint64_t)0x1234567 << 32) | 0x89abcdef;
494  bus->WriteData(data64, BigEndian);
495 
496  bus->AddressSelect(256 + 4);
497 
498  uint32_t data32_b = 0;
499  bus->ReadData(data32_b, LittleEndian);
500 
501  UnitTest::Assert("32-bit read", data32_b, 0xefcdab89);
502 
503  uint16_t data16_b = 0;
504  bus->ReadData(data16_b, LittleEndian);
505 
506  UnitTest::Assert("16-bit read", data16_b, 0xab89);
507 
508  uint8_t data8_b = 0;
509  bus->ReadData(data8_b);
510 
511  UnitTest::Assert("8-bit read", data8_b, 0x89);
512 }
513 
514 static void Test_RAMComponent_WriteProtect()
515 {
517  AddressDataBus* bus = ram->AsAddressDataBus();
518 
519  uint32_t data32 = 0x89abcdef;
520  bus->AddressSelect(256);
521  UnitTest::Assert("non-writeprotected write should succeed",
522  bus->WriteData(data32, BigEndian));
523 
524  uint16_t data16_a = 0;
525  bus->AddressSelect(256 + 2);
526  bus->ReadData(data16_a, BigEndian);
527  UnitTest::Assert("16-bit read", data16_a, 0xcdef);
528 
529  ram->SetVariableValue("writeProtect", "true");
530 
531  data32 = 0x11223344;
532  bus->AddressSelect(256);
533  UnitTest::Assert("writeprotected write should fail",
534  bus->WriteData(data32, BigEndian) == false);
535 
536  data16_a = 0;
537  bus->AddressSelect(256 + 2);
538  bus->ReadData(data16_a, BigEndian);
539  UnitTest::Assert("16-bit read", data16_a, 0xcdef);
540 
541  ram->SetVariableValue("writeProtect", "false");
542 
543  data32 = 0x12345678;
544  bus->AddressSelect(256);
545  UnitTest::Assert("write should succeed again",
546  bus->WriteData(data32, BigEndian));
547 
548  data16_a = 0;
549  bus->AddressSelect(256 + 2);
550  bus->ReadData(data16_a, BigEndian);
551  UnitTest::Assert("16-bit read", data16_a, 0x5678);
552 }
553 
554 static void Test_RAMComponent_ClearOnReset()
555 {
557  AddressDataBus* bus = ram->AsAddressDataBus();
558 
559  uint32_t data32 = 0x89abcdef;
560  bus->AddressSelect(256);
561  bus->WriteData(data32, BigEndian);
562 
563  uint16_t data16_a = 0;
564  bus->AddressSelect(256 + 2);
565  bus->ReadData(data16_a, BigEndian);
566  UnitTest::Assert("16-bit read", data16_a, 0xcdef);
567 
568  ram->Reset();
569 
570  uint16_t data16_b = 0;
571  bus->AddressSelect(256 + 2);
572  bus->ReadData(data16_b, BigEndian);
573  UnitTest::Assert("reset should have cleared RAM", data16_b, 0x0000);
574 }
575 
576 static void Test_RAMComponent_Clone()
577 {
579  AddressDataBus* bus = ram->AsAddressDataBus();
580 
581  uint32_t data32 = 0x89abcdef;
582  bus->AddressSelect(4);
583  bus->WriteData(data32, BigEndian);
584 
585  uint16_t data16_a = 0x1234;
586  bus->AddressSelect(10);
587  bus->WriteData(data16_a, LittleEndian);
588 
589  UnitTest::Assert("serialization/deserialization failed?", ram->CheckConsistency());
590 
591  refcount_ptr<Component> clone = ram->Clone();
592  bus = clone->AsAddressDataBus();
593 
594  data32 = 0x22222222;
595  bus->AddressSelect(4);
596  bus->ReadData(data32, LittleEndian);
597  UnitTest::Assert("32-bit read", data32, 0xefcdab89);
598 
599  data16_a = 0xffff;
600  bus->AddressSelect(10);
601  bus->ReadData(data16_a, BigEndian);
602  UnitTest::Assert("16-bit read", data16_a, 0x3412);
603 }
604 
605 static void Test_RAMComponent_ManualSerialization()
606 {
608  AddressDataBus* bus = ram->AsAddressDataBus();
609 
610  uint32_t data32 = 0x89abcde5;
611  bus->AddressSelect(4);
612  bus->WriteData(data32, BigEndian);
613 
614  uint16_t data16_a = 0x1235;
615  bus->AddressSelect(10);
616  bus->WriteData(data16_a, LittleEndian);
617 
618  SerializationContext context;
619  stringstream ss;
620  ram->Serialize(ss, context);
621 
622  string result = ss.str();
623  size_t pos = 0;
624  stringstream messages;
625  refcount_ptr<Component> ram2 = Component::Deserialize(messages, result, pos);
626  bus = ram2->AsAddressDataBus();
627 
628  data32 = 0x22222222;
629  bus->AddressSelect(4);
630  bus->ReadData(data32, LittleEndian);
631  UnitTest::Assert("32-bit read", data32, 0xe5cdab89);
632 
633  data16_a = 0xffff;
634  bus->AddressSelect(10);
635  bus->ReadData(data16_a, BigEndian);
636  UnitTest::Assert("16-bit read", data16_a, 0x3512);
637 }
638 
639 static void Test_RAMComponent_Methods_Reexecutableness()
640 {
642 
643  UnitTest::Assert("dump method SHOULD be re-executable"
644  " without args", ram->MethodMayBeReexecutedWithoutArgs("dump") == true);
645 
646  UnitTest::Assert("nonexistant method should NOT be re-executable"
647  " without args", ram->MethodMayBeReexecutedWithoutArgs("nonexistant") == false);
648 }
649 
651 {
652  UNITTEST(Test_RAMComponent_AddressDataBus);
653  UNITTEST(Test_RAMComponent_InitiallyZero);
654  UNITTEST(Test_RAMComponent_WriteThenRead);
655  UNITTEST(Test_RAMComponent_WriteThenRead_ReverseEndianness);
656  UNITTEST(Test_RAMComponent_WriteProtect);
657  UNITTEST(Test_RAMComponent_ClearOnReset);
658  UNITTEST(Test_RAMComponent_Clone);
659  UNITTEST(Test_RAMComponent_ManualSerialization);
660  UNITTEST(Test_RAMComponent_Methods_Reexecutableness);
661 }
662 
663 #endif
664 
data
u_short data
Definition: siireg.h:79
AddressDataBus::ReadData
virtual bool ReadData(uint8_t &data, Endianness endianness=BigEndian)=0
Reads 8-bit data from the currently selected address.
Component::AddCustomVariable
bool AddCustomVariable(const string &name, CustomStateVariableHandler *variableHandler)
Adds a custom state variable to the Component.
Definition: Component.h:586
Component::AddVariable
bool AddVariable(const string &name, T *variablePointer)
Adds a state variable of type T to the Component.
Definition: Component.h:563
ComponentFactory.h
GXemul
The main emulator class.
Definition: GXemul.h:55
MemoryMappedComponent
A base-class for memory-mapped components.
Definition: MemoryMappedComponent.h:54
Component::Deserialize
static refcount_ptr< Component > Deserialize(ostream &messages, const string &str, size_t &pos)
Deserializes a string into a component tree.
Definition: Component.cc:1130
LittleEndian
@ LittleEndian
Definition: misc.h:159
RAMComponent::AsAddressDataBus
virtual AddressDataBus * AsAddressDataBus()
Returns the component's AddressDataBus interface.
Definition: RAMComponent.cc:197
RAMComponent::RAMComponent
RAMComponent(const string &visibleClassName="ram")
Constructs a RAMComponent.
Definition: RAMComponent.cc:36
RAMComponent::AddressSelect
virtual void AddressSelect(uint64_t address)
Place an address on the bus.
Definition: RAMComponent.cc:203
refcount_ptr< Component >
RAMComponent::ResetState
virtual void ResetState()
Resets the state variables of this component.
Definition: RAMComponent.cc:85
RAMComponent::ExecuteMethod
virtual void ExecuteMethod(GXemul *gxemul, const string &methodName, const vector< string > &arguments)
Executes a method on the component.
Definition: RAMComponent.cc:111
RAMComponent::WriteData
virtual bool WriteData(const uint8_t &data, Endianness endianness)
Writes 8-bit data to the currently selected address.
Definition: RAMComponent.cc:309
UNITTESTS
#define UNITTESTS(class)
Helper for unit test case execution.
Definition: UnitTest.h:184
LE32_TO_HOST
#define LE32_TO_HOST(x)
Definition: misc.h:180
RAMComponent.h
RAMComponent::MethodMayBeReexecutedWithoutArgs
virtual bool MethodMayBeReexecutedWithoutArgs(const string &methodName) const
Returns whether a method name may be re-executed without args.
Definition: RAMComponent.cc:101
RAMComponent::~RAMComponent
virtual ~RAMComponent()
Definition: RAMComponent.cc:53
BE32_TO_HOST
#define BE32_TO_HOST(x)
Definition: misc.h:181
UNITTEST
#define UNITTEST(functionname)
Helper for unit test case execution.
Definition: UnitTest.h:217
LE64_TO_HOST
#define LE64_TO_HOST(x)
Definition: misc.h:188
Component::GetMethodNames
virtual void GetMethodNames(vector< string > &names) const
Retrieves a component's implemented method names.
Definition: Component.cc:393
UnitTest::Assert
static void Assert(const string &strFailMessage, bool condition)
Asserts that a boolean condition is correct.
Definition: UnitTest.cc:40
AddressDataBus::WriteData
virtual bool WriteData(const uint8_t &data, Endianness endianness=BigEndian)=0
Writes 8-bit data to the currently selected address.
Component::ExecuteMethod
virtual void ExecuteMethod(GXemul *gxemul, const string &methodName, const vector< string > &arguments)
Executes a method on the component.
Definition: Component.cc:406
UI::ShowDebugMessage
virtual void ShowDebugMessage(const string &msg)=0
Shows a debug message.
SerializationContext
A context used during serialization of objects.
Definition: SerializationContext.h:38
RAMComponent::GetAttribute
static string GetAttribute(const string &attributeName)
Get attribute information about the RAMComponent class.
Definition: RAMComponent.cc:76
Endianness
Endianness
Definition: misc.h:157
ComponentFactory::CreateComponent
static refcount_ptr< Component > CreateComponent(const string &componentNameAndOptionalArgs, GXemul *gxemul=NULL)
Creates a component given a short component name.
Definition: ComponentFactory.cc:87
Component::SetVariableValue
bool SetVariableValue(const string &name, const string &expression)
Sets a variable to a new value.
Definition: Component.cc:1030
AddressDataBus::AddressSelect
virtual void AddressSelect(uint64_t address)=0
Place an address on the bus.
RAMComponent::GetMethodNames
virtual void GetMethodNames(vector< string > &names) const
Retrieves a component's implemented method names.
Definition: RAMComponent.cc:91
BE64_TO_HOST
#define BE64_TO_HOST(x)
Definition: misc.h:189
GXemul::GetUI
UI * GetUI()
Gets a pointer to the GXemul instance' active UI.
Definition: GXemul.cc:653
Component::CheckConsistency
bool CheckConsistency() const
Checks consistency by serializing and deserializing the component (including all its child components...
Definition: Component.cc:1226
Component::MethodMayBeReexecutedWithoutArgs
virtual bool MethodMayBeReexecutedWithoutArgs(const string &methodName) const
Returns whether a method name may be re-executed without args.
Definition: Component.cc:399
BE16_TO_HOST
#define BE16_TO_HOST(x)
Definition: misc.h:173
LE16_TO_HOST
#define LE16_TO_HOST(x)
Definition: misc.h:172
AddressDataBus
An interface for implementing components that read/write data via an address bus.
Definition: AddressDataBus.h:45
Component::GetAttribute
static string GetAttribute(const string &attributeName)
Creates a Component.
Definition: Component.cc:66
Component::Serialize
void Serialize(ostream &ss, SerializationContext &context) const
Serializes the Component into a string stream.
Definition: Component.cc:1070
Component::Clone
refcount_ptr< Component > Clone() const
Clones the component and all its children.
Definition: Component.cc:76
BigEndian
@ BigEndian
Definition: misc.h:158
RAMComponent::ReadData
virtual bool ReadData(uint8_t &data, Endianness endianness)
Reads 8-bit data from the currently selected address.
Definition: RAMComponent.cc:240
Component::AsAddressDataBus
virtual AddressDataBus * AsAddressDataBus()
Returns the component's AddressDataBus interface, if any.
Definition: Component.cc:367
RAMComponent
A Random Access Memory Component.
Definition: RAMComponent.h:77
ComponentCreateArgs
Definition: Component.h:49
GXemul.h
Component::Reset
void Reset()
Resets the state of this component and all its children.
Definition: Component.cc:281
RAMComponent::Create
static refcount_ptr< Component > Create(const ComponentCreateArgs &args)
Creates a RAMComponent.
Definition: RAMComponent.cc:70

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