cpu_mips.cc Source File
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34 #include <sys/types.h>
38 #include "../../config.h"
57 static const char *hi6_names[] =
HI6_NAMES;
62 static const char *mmi_names[] =
MMI_NAMES;
73 #define DYNTRANS_DUALMODE_32
74 #define DYNTRANS_DELAYSLOT
90 int cpu_id,
char *cpu_type_name)
92 int i, found, j, tags_size, n_cache_lines, size_per_cache_line;
94 int64_t secondary_cache_size;
100 while (i >= 0 && cpu_type_defs[i].
name != NULL) {
101 if (strcasecmp(cpu_type_defs[i].
name, cpu_type_name) == 0) {
213 size_per_cache_line = 32;
223 tags_size = n_cache_lines * size_per_cache_line;
232 for (j=0; j<n_cache_lines; j++) {
251 secondary_cache_size = 0;
257 debug(
" (I+D = %i+%i KB",
261 if (secondary_cache_size != 0) {
263 if (secondary_cache_size >= 1048576)
265 (secondary_cache_size / 1048576));
268 (secondary_cache_size / 1024));
275 for (i=2; i<8; i++) {
279 memset(&templ, 0,
sizeof(templ));
363 debug(
"\n%i-bit %s-endian (MIPS",
368 case 1:
debug(
" ISA I");
break;
369 case 2:
debug(
" ISA II");
break;
370 case 3:
debug(
" ISA III");
break;
371 case 4:
debug(
" ISA IV");
break;
372 case 5:
debug(
" ISA V");
break;
393 debug(
", direct-mapped");
404 debug(
", direct-mapped");
409 int kb = (1 << ct->
scache) / 1024;
410 debug(
"L2 cache: %i %s",
411 kb >= 1024? kb / 1024 : kb, kb >= 1024?
"MB":
"KB");
417 debug(
", direct-mapped");
436 while (cpu_type_defs[i].
name != NULL) {
438 for (j=10 -
strlen(cpu_type_defs[i].
name); j>0; j--)
441 if ((i % 6) == 0 || cpu_type_defs[i].
name == NULL)
454 uint32_t iword = *((uint32_t *)&ib[0]);
461 switch (iword >> 26) {
463 switch (iword & 0x3f) {
470 switch ((iword >> 16) & 0x1f) {
514 for (i=0; i<m->
ncpus; i++) {
518 if (x >= 0 && i != x)
522 printf(
"cpu%i: (", i);
525 printf(
"index=0x%08x random=0x%08x",
529 printf(
"index=0x%016" PRIx64
530 " random=0x%016" PRIx64,
535 printf(
" wired=0x%" PRIx64,
541 nr_of_tlb_entries; j++) {
544 printf(
" %02x: hi=0x%08" PRIx32
" lo=0x%08"
546 (uint32_t) cop0->
tlbs[j].
hi,
549 printf(
" %02x: hi=0x%08" PRIx32
" mask=0x"
550 "%08" PRIx32
" lo0=0x%08" PRIx32
551 " lo1=0x%08" PRIx32
"\n", j,
552 (uint32_t) cop0->
tlbs[j].
hi,
557 printf(
" %02x: hi=0x%016" PRIx64
" mask="
558 "0x%016" PRIx64
" lo0=0x%016" PRIx64
559 " lo1=0x%016" PRIx64
"\n", j,
560 (uint64_t) cop0->
tlbs[j].
hi,
571 for (i=0; i<m->
ncpus; i++) {
575 if (x >= 0 && i != x)
582 printf(
"cpu%i: (", i);
585 case 2: printf(
"index=0x%x random=0x%x",
591 default:printf(
"index=0x%x random=0x%x",
594 printf(
" wired=0x%" PRIx64,
601 nr_of_tlb_entries; j++) {
602 uint64_t hi = cop0->
tlbs[j].
hi;
603 uint64_t lo0 = cop0->
tlbs[j].
lo0;
604 uint64_t lo1 = cop0->
tlbs[j].
lo1;
608 mask |= (1 << (pageshift+1)) - 1;
611 printf(
" %02x: ", j);
616 printf(
"(invalid)\n");
619 printf(
"vaddr=0x%08x ",
622 printf(
"(global), ");
624 printf(
"(asid %02x),", (
int) ((hi &
627 printf(
" paddr=0x%08x ",
637 printf(
"vaddr=0x%08" PRIx32
" ",
638 (uint32_t) (hi & ~mask));
641 printf(
"vaddr=%016" PRIx64
" ",
642 (uint64_t) (hi & ~mask));
645 printf(
"(global): ");
647 printf(
"(asid %02x):",
653 printf(
" p0=(invalid) ");
658 paddr &= ~(mask >> 1);
659 printf(
" p0=0x%09" PRIx64
" ",
665 printf(
" p1=(invalid) ");
670 paddr &= ~(mask >> 1);
671 printf(
" p1=0x%09" PRIx64
" ",
677 psize = (mask + 1) >> 1;
679 if (psize >= 1024 && psize <= 256*1024)
680 printf(
" (%iKB)", (
int) (psize >> 10));
681 else if (psize >= 1024*1024 && psize <=
683 printf(
" (%iMB)", (
int) (psize >> 20));
709 int running, uint64_t dumpaddr)
711 int hi6, special6, regimm5, sub;
712 int rt, rd, rs, sa, imm, copz, cache_op, which_cache, showtag;
713 uint64_t
addr, offset;
715 unsigned char instr[4];
721 if ((dumpaddr & 3) != 0)
722 printf(
"WARNING: Unaligned address!\n");
726 if (
symbol != NULL && offset==0)
733 debug(
"%08" PRIx32, (uint32_t)dumpaddr);
735 debug(
"%016" PRIx64, (uint64_t)dumpaddr);
737 memcpy(
instr, originstr,
sizeof(uint32_t));
750 debug(
": %02x%02x%02x%02x",
762 hi6 = (
instr[3] >> 2) & 0x3f;
766 special6 =
instr[0] & 0x3f;
777 sub = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
779 rd = (
instr[1] >> 3) & 31;
780 sa = ((
instr[1] & 7) << 2) + ((
instr[0] >> 6) & 3);
790 debug(
"nop (weird, sa=%i)", sa);
796 debug(
"%s\t%s,", special_names[special6],
798 debug(
"%s,%i", regnames[rt], sa);
802 special_rot_names[special6],
804 debug(
"%s,%i", regnames[rt], sa);
806 default:
debug(
"UNIMPLEMENTED special, sub=0x%02x\n",
816 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
818 rd = (
instr[1] >> 3) & 31;
819 sub = ((
instr[1] & 7) << 2) + ((
instr[0] >> 6) & 3);
823 debug(
"%s\t%s", special_names[special6],
825 debug(
",%s", regnames[rt]);
826 debug(
",%s", regnames[rs]);
829 debug(
"%s\t%s", special_rot_names[special6],
831 debug(
",%s", regnames[rt]);
832 debug(
",%s", regnames[rs]);
834 default:
debug(
"UNIMPLEMENTED special, sub=0x%02x\n",
839 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
844 (
instr[1] & 0x04) ?
".hb" :
"",
846 if (running &&
symbol != NULL)
850 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
851 rd = (
instr[1] >> 3) & 31;
856 (
instr[1] & 0x04) ?
".hb" :
"",
858 debug(
",%s", regnames[rs]);
859 if (running &&
symbol != NULL)
864 rd = (
instr[1] >> 3) & 31;
865 debug(
"%s\t%s", special_names[special6], regnames[rd]);
869 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
870 debug(
"%s\t%s", special_names[special6], regnames[rs]);
888 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
890 rd = (
instr[1] >> 3) & 31;
895 debug(
"move\t%s", regnames[rd]);
896 debug(
",%s", regnames[rs]);
901 debug(
"move\t%s", regnames[rd]);
902 debug(
",%s", regnames[rt]);
904 debug(
"%s\t%s", special_names[special6],
906 debug(
",%s", regnames[rs]);
907 debug(
",%s", regnames[rt]);
918 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
920 rd = (
instr[1] >> 3) & 31;
921 debug(
"%s\t", special_names[special6]);
926 debug(
"%s,", regnames[rd]);
928 debug(
"WEIRD_R5900_RD,");
930 debug(
"WEIRD_RD_NONZERO,");
933 debug(
"%s", regnames[rs]);
934 debug(
",%s", regnames[rt]);
942 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
945 debug(
"%s\t", special_names[special6]);
946 debug(
"%s", regnames[rs]);
947 debug(
",%s", regnames[rt]);
952 imm = ((
instr[1] & 7) << 2) + (
instr[0] >> 6);
953 debug(
"sync\t0x%02x", imm);
959 debug(
"syscall\t0x%05x", imm);
967 debug(
"break\t0x%05x", imm);
973 rd = (
instr[1] >> 3) & 31;
974 debug(
"mfsa\t%s", regnames[rd]);
976 debug(
"unimplemented special 0x28");
981 rs = ((
instr[3] & 3) << 3) +
982 ((
instr[2] >> 5) & 7);
983 debug(
"mtsa\t%s", regnames[rs]);
985 debug(
"unimplemented special 0x29");
989 debug(
"%s\t= UNIMPLEMENTED", special_names[special6]);
1000 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1005 addr = (dumpaddr + 4) + (imm << 2);
1011 debug(
"%s\t", hi6_names[hi6]);
1017 debug(
"%s,", regnames[rt]);
1019 debug(
"%s,", regnames[rs]);
1041 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1046 debug(
"%s\t%s,", hi6_names[hi6], regnames[rt]);
1047 debug(
"%s,", regnames[rs]);
1049 debug(
"0x%04x", imm & 0xffff);
1056 debug(
"lui\t%s,0x%x", regnames[rt], imm);
1095 debug(
"mdmx\t(UNIMPLEMENTED)");
1100 int msbd, lsb, sub10;
1101 special6 =
instr[0] & 0x3f;
1102 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1104 rd = msbd = (
instr[1] >> 3) & 31;
1105 lsb = ((
instr[1] & 7) << 2) | (
instr[0] >> 6);
1106 sub10 = (rs << 5) | lsb;
1114 debug(
"%s", special3_names[special6]);
1119 debug(
"\t%s", regnames[rt]);
1120 debug(
",%s", regnames[rs]);
1121 debug(
",%i,%i", lsb, msbd + 1);
1128 debug(
"%s", special3_names[special6]);
1136 debug(
"\t%s", regnames[rt]);
1137 debug(
",%s", regnames[rs]);
1138 debug(
",%i,%i", lsb, msbd + 1);
1151 debug(
"\t%s", regnames[rd]);
1152 debug(
",%s", regnames[rt]);
1154 default:
debug(
"%s", special3_names[special6]);
1155 debug(
"\t(UNIMPLEMENTED)");
1167 debug(
"\t%s", regnames[rd]);
1168 debug(
",%s", regnames[rt]);
1170 default:
debug(
"%s", special3_names[special6]);
1171 debug(
"\t(UNIMPLEMENTED)");
1176 debug(
"%s", special3_names[special6]);
1177 debug(
"\t%s", regnames[rt]);
1178 debug(
",hwr%i", rd);
1181 default:
debug(
"%s", special3_names[special6]);
1182 debug(
"\t(UNIMPLEMENTED)");
1187 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1198 debug(
"pref\t0x%x,%i(%s)",
1199 rt, imm, regnames[rs]);
1202 debug(
"\t[0x%016" PRIx64
" = %s]",
1211 debug(
"%s\t", hi6_names[hi6]);
1219 debug(
"%s", regnames[rt]);
1221 debug(
",%i(%s)", imm, regnames[rs]);
1227 debug(
"0x%08" PRIx32,
1230 debug(
"0x%016" PRIx64,
1246 imm = (((
instr[3] & 3) << 24) + (
instr[2] << 16) +
1248 addr = (dumpaddr + 4) & ~((1 << 28) - 1);
1252 debug(
"%s\t0x", hi6_names[hi6]);
1267 imm &= ((1 << 26) - 1);
1272 return sizeof(instrword);
1275 rt = ((
instr[3] & 3) << 3) + (
instr[2] >> 5);
1276 copz =
instr[2] & 31;
1278 cache_op = copz >> 2;
1279 which_cache = copz & 3;
1281 debug(
"cache\t0x%02x,0x%04x(%s)", copz, imm, regnames[rt]);
1282 if (which_cache==0)
debug(
" [ primary I-cache");
1283 if (which_cache==1)
debug(
" [ primary D-cache");
1284 if (which_cache==2)
debug(
" [ secondary I-cache");
1285 if (which_cache==3)
debug(
" [ secondary D-cache");
1287 if (cache_op==0)
debug(
"index invalidate");
1288 if (cache_op==1)
debug(
"index load tag");
1289 if (cache_op==2)
debug(
"index store tag"), showtag=1;
1290 if (cache_op==3)
debug(
"create dirty exclusive");
1291 if (cache_op==4)
debug(
"hit invalidate");
1292 if (cache_op==5)
debug(
"fill OR hit writeback invalidate");
1293 if (cache_op==6)
debug(
"hit writeback");
1294 if (cache_op==7)
debug(
"hit set virtual");
1296 debug(
", addr 0x%016" PRIx64,
1299 debug(
", taghi=%08lx lo=%08lx",
1306 special6 =
instr[0] & 0x3f;
1307 instrword = (
instr[3] << 24) + (
instr[2] << 16) +
1309 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1311 rd = (
instr[1] >> 3) & 31;
1314 int c790mmifunc = (instrword >> 6) & 0x1f;
1317 debug(
"%s\t", mmi_names[special6]);
1324 debug(
"%s,", regnames[rd]);
1326 debug(
"%s,%s", regnames[rs], regnames[rt]);
1330 debug(
"%s\t", mmi0_names[c790mmifunc]);
1331 switch (c790mmifunc) {
1341 debug(
"%s,%s,%s", regnames[rd],
1342 regnames[rs], regnames[rt]);
1345 default:
debug(
"(UNIMPLEMENTED)");
1350 debug(
"%s\t", mmi1_names[c790mmifunc]);
1351 switch (c790mmifunc) {
1358 debug(
"%s,%s,%s", regnames[rd],
1359 regnames[rs], regnames[rt]);
1362 default:
debug(
"(UNIMPLEMENTED)");
1367 debug(
"%s\t", mmi2_names[c790mmifunc]);
1368 switch (c790mmifunc) {
1372 debug(
"%s", regnames[rd]);
1385 debug(
"%s,%s,%s", regnames[rd],
1386 regnames[rs], regnames[rt]);
1389 default:
debug(
"(UNIMPLEMENTED)");
1394 debug(
"%s\t", mmi3_names[c790mmifunc]);
1395 switch (c790mmifunc) {
1399 debug(
"%s", regnames[rs]);
1408 debug(
"%s,%s,%s", regnames[rd],
1409 regnames[rs], regnames[rt]);
1412 default:
debug(
"(UNIMPLEMENTED)");
1416 default:
debug(
"(UNIMPLEMENTED)");
1422 debug(
"%s\t", special2_names[special6]);
1431 debug(
"WEIRD_NONZERO_RD(%s),",
1434 debug(
"%s,%s", regnames[rs], regnames[rt]);
1439 debug(
"%s,%s,%s", regnames[rd],
1440 regnames[rs], regnames[rt]);
1447 debug(
"%s,%s", regnames[rd], regnames[rs]);
1451 debug(
"(UNIMPLEMENTED)");
1456 regimm5 =
instr[2] & 0x1f;
1457 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1472 debug(
"%s\t%s,", regimm_names[regimm5], regnames[rs]);
1474 addr = (dumpaddr + 4) + (imm << 2);
1479 debug(
"0x%016" PRIx64, (uint64_t)
addr);
1488 debug(
"%s\t%s,", regimm_names[regimm5], regnames[rs]);
1491 debug(
"0x%" PRIx32, (uint32_t) imm);
1493 debug(
"0x%" PRIx64, (uint64_t) imm);
1497 debug(
"%s\t%i(%s)", regimm_names[regimm5],
1502 debug(
"unimplemented regimm5 = 0x%02x", regimm5);
1506 debug(
"unimplemented hi6 = 0x%02x", hi6);
1511 return sizeof(instrword);
1525 int coprocnr, i, bits32;
1538 debug(
"cpu%i: pc = %08" PRIx32,
1541 debug(
"cpu%i: pc=%016" PRIx64,
1544 debug(
"cpu%i: pc = 0x%016" PRIx64,
1551 debug(
"cpu%i: hi = %08" PRIx32
" lo = %08" PRIx32
"\n",
1555 debug(
"cpu%i: hi=%016" PRIx64
"%016" PRIx64
" lo="
1556 "%016" PRIx64
"%016" PRIx64
"\n",
cpu->
cpu_id,
1560 debug(
"cpu%i: hi = 0x%016" PRIx64
" lo = 0x%016"
1569 for (i=0; i<32; i++) {
1570 int r = (i >> 1) + ((i & 1) << 4);
1577 debug(
" %3s=%016" PRIx64
"%016" PRIx64,
1578 regnames[r], (uint64_t)
1584 }
else if (bits32) {
1586 for (i=0; i<32; i++) {
1592 debug(
" %3s = %08" PRIx32, regnames[i],
1599 for (i=0; i<32; i++) {
1600 int r = (i >> 1) + ((i & 1) << 4);
1606 debug(
" %3s = 0x%016" PRIx64,
1615 for (coprocnr=0; coprocnr<4; coprocnr++) {
1621 if (!(coprocs & (1<<coprocnr)))
1624 debug(
"cpu%i: no coprocessor %i\n",
1630 for (i=0; i<32; i++) {
1636 debug(
" %8s", cop0_names[i]);
1638 debug(
" c%i,%02i", coprocnr, i);
1642 coproc[coprocnr]->reg[i]);
1651 debug(
" = 0x%016" PRIx64, (uint64_t)
1656 if ((i & nm1) == nm1)
1667 debug(
"config_select1 = 0x");
1672 debug(
"%016" PRIx64,
1678 if (coprocnr == 1) {
1679 for (i=0; i<32; i++)
1682 printf(
"cpu%i: fcr0 (fcir) = 0x%08x\n",
1684 coproc[coprocnr]->fcr[i]);
1687 printf(
"cpu%i: fcr25 (fccr) = 0x%08x\n",
1689 coproc[coprocnr]->fcr[i]);
1692 printf(
"cpu%i: fcr31 (fcsr) = 0x%08x\n",
1694 coproc[coprocnr]->fcr[i]);
1701 printf(
"cpu%i: Read-Modify-Write in progress, address "
1741 int coproc_nr, uint64_t vaddr_vpn2,
int vaddr_asid,
int x_64)
1754 cpu->
pc +=
sizeof(uint32_t);
1767 debug(
"exception %s%s",
1768 exception_names[exccode], tlb?
" <tlb>" :
"");
1773 debug(
" cause_im=0x%02x", (
int)
1780 for (x=0; x<4; x++) {
1784 if (d > -256 && d < 256) {
1785 debug(
" a%i=%i", x, (
int)d);
1788 debug(
" a%i=\"%s\"", x,
1790 d, strbuf,
sizeof(strbuf)));
1793 debug(
" a%i=0x%" PRIx32, x,
1796 debug(
" a%i=0x%" PRIx64, x,
1803 debug(
" coproc_nr=%i", coproc_nr);
1808 debug(
" vaddr=0x%08x", (
int)vaddr);
1810 debug(
" vaddr=0x%016" PRIx64, (uint64_t)vaddr);
1814 debug(
" pc=0x%08" PRIx32
" ", (uint32_t)
cpu->
pc);
1816 debug(
" pc=0x%016" PRIx64
" ", (uint64_t)
cpu->
pc);
1824 if (tlb && vaddr < 0x1000) {
1831 fatal(
"warning: LOW reference: vaddr=");
1833 fatal(
"0x%08" PRIx32, (uint32_t) vaddr);
1835 fatal(
"0x%016" PRIx64, (uint64_t) vaddr);
1836 fatal(
", exception %s, pc=", exception_names[exccode]);
1845 if (exc_model ==
EXC3K)
1863 if (exc_model ==
EXC3K) {
1915 fatal(
"[ huh? vaddr_asid 0x%02x not same as in ENTRYHI 0x%02x ]\n",
1952 base = 0xffffffffbfc00200ULL;
1954 base = 0xffffffff80000000ULL;
1956 switch (exc_model) {
1959 if (tlb && !(vaddr & 0x80000000ULL) &&
1961 cpu->
pc = base + 0x000;
1963 cpu->
pc = base + 0x080;
1980 cpu->
pc = base + 0x080;
1982 cpu->
pc = base + 0x000;
1986 cpu->
pc = base + 0x200;
1988 cpu->
pc = base + 0x180;
1992 if (exc_model ==
EXC3K) {
uint64_t gpr_quadhi[N_MIPS_GPRS]
struct mips_cpu_type_def cpu_type
uint64_t reg[N_MIPS_COPROC_REGS]
struct mips_coproc * coproc[N_MIPS_COPROCS]
#define XCONTEXT_BADVPN2_SHIFT
#define INTERRUPT_CONNECT(name, istruct)
#define MIPS_REGISTER_NAMES
void(* interrupt_deassert)(struct interrupt *)
struct symbol_context symbol_context
int cache_secondary_linesize
#define CONTEXT_BADVPN2_SHIFT
char * get_symbol_name(struct symbol_context *, uint64_t addr, uint64_t *offset)
#define XCONTEXT_BADVPN2_MASK
#define CAUSE_EXCCODE_SHIFT
int mips32_run_instr(struct cpu *cpu)
#define N_MIPS_COPROC_REGS
void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, uint32_t function, int unassemble_only, int running)
void mips_cpu_list_available_types(void)
#define R2K3K_RANDOM_MASK
#define CAUSE_EXCCODE_MASK
int(* instruction_has_delayslot)(struct cpu *cpu, unsigned char *ib)
struct mips_coproc * mips_coproc_new(struct cpu *cpu, int coproc_nr)
int cache_picache_linesize
void(* update_translation_table)(struct cpu *, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
uint64_t cache_last_paddr[2]
#define R2K3K_CONTEXT_BADVPN_SHIFT
void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
#define ENTRYHI_VPN2_MASK_R10K
#define CPU_SETTINGS_ADD_REGISTER64(name, var)
#define R2K3K_CONTEXT_BADVPN_MASK
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
#define DEFAULT_PCACHE_SIZE
void(* invalidate_code_translation)(struct cpu *, uint64_t paddr, int flags)
int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
int mips_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, int cpu_id, char *cpu_type_name)
void COMBINE() strlen(struct cpu *cpu, struct arm_instr_call *ic, int low_addr)
void fatal(const char *fmt,...)
void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
void mips_pc_to_pointers(struct cpu *)
#define R2K3K_CAUSE_EXCCODE_MASK
int mips_run_instr(struct cpu *cpu)
#define CACHE_INSTRUCTION
#define R2K3K_RANDOM_SHIFT
int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define ENTRYHI_VPN2_MASK
void mips32_pc_to_pointers(struct cpu *)
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
int(* translate_v2p)(struct cpu *, uint64_t vaddr, uint64_t *return_paddr, int flags)
struct interrupt irq_compare
void mips_cpu_dumpinfo(struct cpu *cpu)
void mips_cpu_interrupt_deassert(struct interrupt *interrupt)
#define R2K3K_ENTRYHI_ASID_SHIFT
#define R2K3K_ENTRYHI_ASID_MASK
#define EMUL_LITTLE_ENDIAN
uint64_t cop0_config_select1
#define MIPS_CPU_TYPE_DEFS
int cache_pdcache_linesize
#define CONTEXT_BADVPN2_MASK_R4100
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
int store_32bit_word(struct cpu *cpu, uint64_t addr, uint64_t data32)
#define R2K3K_INDEX_SHIFT
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *originstr, int running, uint64_t dumpaddr)
#define CONTEXT_BADVPN2_MASK
#define INITIAL_STACK_POINTER
uint64_t gpr[N_MIPS_GPRS]
int(* run_instr)(struct cpu *cpu)
#define DEBUG_INDENTATION
int memory_points_to_string(struct cpu *cpu, struct memory *mem, uint64_t addr, int min_string_length)
void(* interrupt_assert)(struct interrupt *)
void interrupt_handler_register(struct interrupt *templ)
#define R2K3K_ENTRYHI_VPN_MASK
void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
#define R2K3K_ENTRYLO_PFN_MASK
void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
#define SPECIAL_ROT_NAMES
int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define EXCEPTION_IN_DELAY_SLOT
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag)
#define ENTRYLO_PFN_SHIFT
char * memory_conv_to_string(struct cpu *cpu, struct memory *mem, uint64_t addr, char *buf, int bufsize)
#define DEFAULT_PCACHE_LINESIZE
void mips_cpu_interrupt_assert(struct interrupt *interrupt)
void debug_indentation(int diff)
int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define CHECK_ALLOCATION(ptr)
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