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if_mecreg.h
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1 /* gxemul: $Id: if_mecreg.h,v 1.2 2005-03-05 12:34:02 debug Exp $ */
2 /* $NetBSD: if_mecreg.h,v 1.4 2008/08/07 15:05:02 tsutsui Exp $ */
3 
4 #ifndef IF_MECREG_H
5 #define IF_MECREG_H
6 
7 /*
8  * Copyright (c) 2001 Christopher Sekiya
9  * Copyright (c) 2000 Soren S. Jorvang
10  * All rights reserved.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  * notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  * notice, this list of conditions and the following disclaimer in the
19  * documentation and/or other materials provided with the distribution.
20  * 3. All advertising materials mentioning features or use of this software
21  * must display the following acknowledgement:
22  * This product includes software developed for the
23  * NetBSD Project. See http://www.NetBSD.org/ for
24  * information about NetBSD.
25  * 4. The name of the author may not be used to endorse or promote products
26  * derived from this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
29  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
30  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
31  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
32  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
33  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
37  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  */
39 
40 /*
41  * MACE MAC110 ethernet register definitions
42  */
43 
44 #define MEC_MAC_CONTROL 0x00
45 #define MEC_MAC_CORE_RESET 0x0000000000000001 /* reset signal */
46 #define MEC_MAC_FULL_DUPLEX 0x0000000000000002 /* 1 to enable */
47 #define MEC_MAC_INT_LOOPBACK 0x0000000000000004 /* 0 = normal op */
48 #define MEC_MAC_SPEED_SELECT 0x0000000000000008 /* 0/1 10/100 */
49 #define MEC_MAC_MII_SELECT 0x0000000000000010 /* MII/SIA */
50 #define MEC_MAC_FILTER_MASK 0x0000000000000060
51 #define MEC_MAC_FILTER_STATION 0x0000000000000000
52 #define MEC_MAC_FILTER_MATCHMULTI 0x0000000000000020
53 #define MEC_MAC_FILTER_ALLMULTI 0x0000000000000040
54 #define MEC_MAC_FILTER_PROMISC 0x0000000000000060
55 #define MEC_MAC_LINK_FAILURE 0x0000000000000080
56 #define MEC_MAC_IPGT 0x0000000000007f00 /* interpacket gap */
57 #define MEC_MAC_IPGT_SHIFT 8
58 #define MEC_MAC_IPGR1 0x00000000003f8000
59 #define MEC_MAC_IPGR1_SHIFT 15
60 #define MEC_MAC_IPGR2 0x000000001fc00000
61 #define MEC_MAC_IPGR2_SHIFT 22
62 #define MEC_MAC_REVISION 0x00000000e0000000
63 #define MEC_MAC_REVISION_SHIFT 29
64 
65 #define MEC_MAC_IPG_DEFAULT \
66  (21 << MEC_MAC_IPGT_SHIFT) | \
67  (17 << MEC_MAC_IPGR1_SHIFT) | \
68  (11 << MEC_MAC_IPGR2_SHIFT)
69 
70 #define MEC_INT_STATUS 0x08
71 #define MEC_INT_STATUS_MASK 0x00000000000000ff
72 #define MEC_INT_TX_EMPTY 0x0000000000000001
73 #define MEC_INT_TX_PACKET_SENT 0x0000000000000002
74 #define MEC_INT_TX_LINK_FAIL 0x0000000000000004
75 #define MEC_INT_TX_MEM_ERROR 0x0000000000000008
76 #define MEC_INT_TX_ABORT 0x0000000000000010
77 #define MEC_INT_RX_THRESHOLD 0x0000000000000020
78 #define MEC_INT_RX_FIFO_UNDERFLOW 0x0000000000000040
79 #define MEC_INT_RX_DMA_UNDERFLOW 0x0000000000000080
80 #define MEC_INT_RX_MCL_FIFO_ALIAS 0x0000000000001f00
81 #define MEC_INT_RX_MCL_FIFO_SHIFT 8
82 #define MEC_INT_TX_RING_BUFFER_ALIAS 0x0000000001ff0000
83 #define MEC_INT_TX_RING_BUFFER_SHIFT 16
84 #define MEC_INT_RX_SEQUENCE_NUMBER 0x000000003e000000
85 #define MEC_INT_MCAST_HASH_OUTPUT 0x0000000040000000
86 
87 #define MEC_DMA_CONTROL 0x10
88 #define MEC_DMA_TX_INT_ENABLE 0x0000000000000001
89 #define MEC_DMA_TX_DMA_ENABLE 0x0000000000000002
90 #define MEC_DMA_TX_RING_SIZE_MASK 0x000000000000000c
91 #define MEC_DMA_RX_INT_THRESHOLD 0x00000000000001f0
92 #define MEC_DMA_RX_INT_THRESH_SHIFT 4
93 #define MEC_DMA_RX_INT_ENABLE 0x0000000000000200
94 #define MEC_DMA_RX_RUNT 0x0000000000000400
95 #define MEC_DMA_RX_PACKET_GATHER 0x0000000000000800
96 #define MEC_DMA_RX_DMA_OFFSET 0x0000000000007000
97 #define MEC_DMA_RX_DMA_OFFSET_SHIFT 12
98 #define MEC_DMA_RX_DMA_ENABLE 0x0000000000008000
99 
100 #define MEC_TIMER 0x18
101 #define MEC_TX_ALIAS 0x20
102 #define MEC_TX_ALIAS_INT_ENABLE 0x0000000000000001
103 
104 #define MEC_RX_ALIAS 0x28
105 #define MEC_RX_ALIAS_INT_ENABLE 0x0000000000000200
106 #define MEC_RX_ALIAS_INT_THRESHOLD 0x00000000000001f0
107 
108 #define MEC_TX_RING_PTR 0x30
109 #define MEC_TX_RING_WRITE_PTR 0x00000000000001ff
110 #define MEC_TX_RING_READ_PTR 0x0000000001ff0000
111 #define MEC_TX_RING_PTR_ALIAS 0x38
112 
113 #define MEC_RX_FIFO 0x40
114 #define MEC_RX_FIFO_ELEMENT_COUNT 0x000000000000001f
115 #define MEC_RX_FIFO_READ_PTR 0x0000000000000f00
116 #define MEC_RX_FIFO_GEN_NUMBER 0x0000000000001000
117 #define MEC_RX_FIFO_WRITE_PTR 0x00000000000f0000
118 #define MEC_RX_FIFO_GEN_NUMBER_2 0x0000000000100000
119 
120 #define MEC_RX_FIFO_ALIAS1 0x48
121 #define MEC_RX_FIFO_ALIAS2 0x50
122 #define MEC_TX_VECTOR 0x58
123 #define MEC_IRQ_VECTOR 0x58
124 
125 #define MEC_PHY_DATA 0x60
126 #define MEC_PHY_DATA_BUSY 0x00010000
127 #define MEC_PHY_DATA_VALUE 0x0000ffff
128 
129 #define MEC_PHY_ADDRESS 0x68
130 #define MEC_PHY_ADDR_REGISTER 0x0000001f
131 #define MEC_PHY_ADDR_DEVICE 0x000003e0
132 #define MEC_PHY_ADDR_DEVSHIFT 5
133 
134 #define MEC_PHY_READ_INITIATE 0x70
135 #define MEC_PHY_BACKOFF 0x78
136 
137 #define MEC_STATION 0xa0
138 #define MEC_STATION_ALT 0xa8
139 #define MEC_STATION_MASK 0x0000ffffffffffffULL
140 
141 #define MEC_MULTICAST 0xb0
142 #define MEC_TX_RING_BASE 0xb8
143 #define MEC_TX_PKT1_CMD_1 0xc0
144 #define MEC_TX_PKT1_BUFFER_1 0xc8
145 #define MEC_TX_PKT1_BUFFER_2 0xd0
146 #define MEC_TX_PKT1_BUFFER_3 0xd8
147 #define MEC_TX_PKT2_CMD_1 0xe0
148 #define MEC_TX_PKT2_BUFFER_1 0xe8
149 #define MEC_TX_PKT2_BUFFER_2 0xf0
150 #define MEC_TX_PKT2_BUFFER_3 0xf8
151 
152 #define MEC_MCL_RX_FIFO 0x100
153 
154 #endif /* IF_MECREG_H */

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