RISCV_CPUComponent.cc Source File

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RISCV_CPUComponent.cc
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1 /*
2  * Copyright (C) 2019 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <assert.h>
29 #include <stdio.h>
30 #include <string.h>
31 #include <iomanip>
32 
33 #include "ComponentFactory.h"
34 #include "GXemul.h"
36 
37 
39  : CPUDyntransComponent("riscv_cpu", "RISCV")
40 {
41  m_frequency = 25e6;
42  m_isBigEndian = false;
43 
44  m_model = "RV64G";
45  m_extensions = RISCV_EXTENSION_I;
46 
47  ResetState();
48 
49  AddVariable("model", &m_model);
50 
51  for (size_t i = 0; i < N_RISCV_XREGS; i++) {
52  AddVariable(RISCV_regnames[i], &m_x[i]);
53  }
54 }
55 
56 
58 {
59  // Defaults:
61  settings["model"] = "RV64G";
62 
64  return NULL;
65 
67  if (!cpu->SetVariableValue("model", "\"" + settings["model"] + "\""))
68  return NULL;
69 
70  return cpu;
71 }
72 
73 
75 {
76  m_pageSize = 4096;
77 
78  for (size_t i=0; i<N_RISCV_XREGS; i++)
79  m_x[i] = 0;
80 
81  m_pc = 0;
82 
84 }
85 
86 
88 {
89  if (m_pc & 0x1) {
90  gxemul->GetUI()->ShowDebugMessage(this, "the pc register"
91  " can not have bit 0 set!\n");
92  return false;
93  }
94 
96 }
97 
98 
99 bool RISCV_CPUComponent::CheckVariableWrite(StateVariable& var, const string& oldValue)
100 {
101  // UI* ui = GetUI();
102 
103  return CPUDyntransComponent::CheckVariableWrite(var, oldValue);
104 }
105 
106 
107 void RISCV_CPUComponent::ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const
108 {
109  stringstream ss;
110 
111  ss.flags(std::ios::hex);
112  ss << " pc = 0x" << std::setfill('0') << std::setw(16) << (uint32_t)m_pc;
113 
114  string symbol = GetSymbolRegistry().LookupAddress(m_pc, true);
115  if (symbol != "")
116  ss << " <" << symbol << ">";
117  ss << "\n";
118 
119  for (size_t i = 0; i < N_RISCV_XREGS; i++) {
120  ss << std::setfill(' ') << std::setw(4) << RISCV_regnames[i]
121  << " = 0x" << std::setfill('0') << std::setw(16) << m_x[i];
122  if ((i&3) == 3)
123  ss << "\n";
124  else
125  ss << " ";
126  }
127 
128  gxemul->GetUI()->ShowDebugMessage(ss.str());
129 }
130 
131 
133 {
134  return 8;
135 }
136 
137 
139 {
140  return m_x[10 + n];
141 }
142 
143 
145 {
146  retval = m_x[10];
147  return true;
148 }
149 
150 
152 {
153  // A "parcel" is 16 bits (shift = 1). Most instructions are 32 bits
154  // wide, but it varies.
155  return 1;
156 }
157 
158 
160 {
161  return instr_ToBeTranslated;
162 }
163 
164 
165 bool RISCV_CPUComponent::VirtualToPhysical(uint64_t vaddr, uint64_t& paddr,
166  bool& writable)
167 {
168  paddr = vaddr;
169  writable = true;
170  return true;
171 }
172 
173 
175 {
176  return pc;
177 }
178 
179 
180 size_t RISCV_CPUComponent::DisassembleInstruction(uint64_t vaddr, vector<string>& result)
181 {
182  uint16_t iwords[RISCV_MAX_PARCELS];
183 
184  AddressSelect(vaddr);
185  bool readOk = ReadData(iwords[0], m_isBigEndian? BigEndian : LittleEndian);
186  int nparcels = 0;
187  if (readOk) {
188  /*
189  * Figure out RISC-V instruction length from the first
190  * 16-bit "parcel" (which may be a whole or a partial instruction):
191  *
192  * xxxxxxxxxxxxxxaa aa != 11 16-bit (1 parcel)
193  * xxxxxxxxxxxbbb11 bbb != 111 32-bit (2 parcels)
194  * xxxxxxxxxx011111 48-bit (3 parcels)
195  * xxxxxxxxx0111111 64-bit (4 parcels)
196  * xnnnxxxxx1111111 nnn != 111 (80+16*nnn)-bit
197  * x111xxxxx1111111 >= 192 bit
198  */
199 
200  int aa = iwords[0] & 3, bbb = (iwords[0] >> 2) & 7;
201 
202  nparcels = 1;
203 
204  if (aa == 3) {
205  nparcels = 2;
206  if (bbb == 7) {
207  nparcels = 3;
208  if (iwords[0] & 0x20) {
209  nparcels = 4;
210  if (iwords[0] & 0x40) {
211  int nnn = (iwords[0] >> 12) & 7;
212  nparcels = 5 + nnn;
213 
214  if (nparcels > RISCV_MAX_PARCELS) {
215  result.push_back("too many parcels in instruction");
216  nparcels = 0;
217  }
218  }
219  }
220  }
221  }
222 
223  int instructionParcelsSuccessfullyRead = 1;
224  for (int i = 1; i < nparcels; ++i) {
225  AddressSelect(vaddr + i * sizeof(uint16_t));
226  if (ReadData(iwords[i], m_isBigEndian? BigEndian : LittleEndian))
227  instructionParcelsSuccessfullyRead ++;
228  }
229 
230  if (instructionParcelsSuccessfullyRead != nparcels)
231  nparcels = 0;
232  }
233 
234  if (nparcels == 0) {
235  result.push_back("instruction could not be read");
236  return 0;
237  }
238 
239  stringstream ssHex;
240  ssHex.flags(std::ios::hex);
241  for (int i = nparcels-1; i >= 0; --i)
242  ssHex << std::setfill('0') << std::setw(4) << (uint32_t) iwords[i];
243 
244  result.push_back(ssHex.str());
245 
246 
247  stringstream ssOpcode;
248  stringstream ssArgs;
249  stringstream ssComments;
250 
251 
252  /*
253  * See this URL for a nice ordered list of all RISC-V instructions:
254  *
255  * https://github.com/rv8-io/rv8/blob/master/doc/pdf/riscv-instructions.pdf
256  */
257 
258  int opcode = iwords[0] & 0x7f;
259  int rd = (iwords[0] >> 7) & 31;
260  uint64_t requiredExtension = 0;
261 
262  /*
263  * RV32I Base Integer Instruction Set:
264  */
265  // TYPE-U:
266  // TYPE-UJ:
267  if (opcode == 0x6f) {
268  // jal
269  int32_t simm = ((iwords[1] & 0x8000) << 5);
270  simm |= ((iwords[1] & 0x7fe0) >> 4);
271  simm |= ((iwords[1] & 0x0010) << 7);
272  simm |= ((iwords[1] & 0x000f) << 16);
273  simm |= ((iwords[0] & 0xf000) << 0);
274  simm <<= 11;
275  simm >>= 11;
276  ssOpcode << (rd ? "jal" : "j");
277  if (rd)
278  ssArgs << RISCV_regnames[rd] << ",";
279  uint64_t addr = vaddr + simm;
280  ssArgs.flags(std::ios::hex | std::ios::showbase);
281  ssArgs << std::setfill('0') << addr;
282  string symbol = GetSymbolRegistry().LookupAddress(addr, true);
283  if (symbol != "")
284  ssArgs << " <" + symbol + ">";
285  requiredExtension = RISCV_EXTENSION_I;
286  }
287  // TYPE-I:
288  // TYPE-SB:
289  // TYPE-S:
290  // TYPE-R:
291 
292  else {
293  ssOpcode << "unknown main opcode 0x";
294  ssOpcode.flags(std::ios::hex);
295  ssOpcode << std::setfill('0') << std::setw(2) << (int)opcode;
296  }
297 
298 
299  result.push_back(ssOpcode.str());
300  result.push_back(ssArgs.str());
301 
302  string comments = ssComments.str();
303  if (comments.length() > 0)
304  result.push_back(comments);
305 
306  if ((m_extensions & requiredExtension) != requiredExtension) {
307  if (comments.length() == 0)
308  result.push_back("");
309 
310  result.push_back("; extension not implemented by this CPU");
311  }
312 
313  return sizeof(uint16_t) * nparcels;
314 }
315 
316 
317 string RISCV_CPUComponent::GetAttribute(const string& attributeName)
318 {
319  if (attributeName == "description")
320  return "RISC-V processor.";
321 
322  return Component::GetAttribute(attributeName);
323 }
324 
325 
326 /*****************************************************************************/
327 
328 
329 /*
330 DYNTRANS_INSTR(RISCV_CPUComponent,b)
331 {
332  DYNTRANS_INSTR_HEAD(RISCV_CPUComponent)
333  cpu->m_pc = ic->arg[0].u32;
334  cpu->DyntransPCtoPointers();
335 }
336 
337 
338 DYNTRANS_INSTR(RISCV_CPUComponent,lda_displacement)
339 {
340  DYNTRANS_INSTR_HEAD(RISCV_CPUComponent)
341  REG32(ic->arg[2]) = ic->arg[0].u32;
342  cpu->m_nextIC = ic + 2;
343 }
344 
345 
346 DYNTRANS_INSTR(RISCV_CPUComponent,mov_lit_reg)
347 {
348  REG32(ic->arg[2]) = ic->arg[0].u32;
349 }
350 */
351 
352 
353 /*****************************************************************************/
354 
355 
356 void RISCV_CPUComponent::Translate(uint16_t iwords[], int nparcels, struct DyntransIC* ic)
357 {
358  UI* ui = GetUI(); // for debug messages
359 
360 // TODO:
361  unsigned int opcode = iwords[0];
362 
363  if (ic->f == NULL && ui != NULL) {
364  stringstream ss;
365  ss.flags(std::ios::hex);
366  ss << "unimplemented opcode 0x" << opcode;
367  ui->ShowDebugMessage(this, ss.str());
368  }
369 }
370 
371 
373 {
375 
376  cpu->DyntransToBeTranslatedBegin(ic);
377 
378  uint16_t iwords[RISCV_MAX_PARCELS];
379  if (cpu->DyntransReadInstruction(iwords[0])) {
380  // See DisassembleInstruction for details about the length.
381  int aa = iwords[0] & 3, bbb = (iwords[0] >> 2) & 7;
382  int nparcels = 1;
383  if (aa == 3) {
384  nparcels = 2;
385  if (bbb == 7) {
386  nparcels = 3;
387  if (iwords[0] & 0x20) {
388  nparcels = 4;
389  if (iwords[0] & 0x40) {
390  int nnn = (iwords[0] >> 12) & 7;
391  nparcels = 5 + nnn;
392 
393  if (nparcels > RISCV_MAX_PARCELS) {
394  UI* ui = cpu->GetUI();
395  ui->ShowDebugMessage(cpu, "too many parcels in instruction");
396  nparcels = 0;
397  }
398  }
399  }
400  }
401  }
402 
403  int instructionParcelsSuccessfullyRead = 1;
404  for (int i = 1; i < nparcels; ++i) {
405  if (cpu->DyntransReadInstruction(iwords[i], sizeof(iwords[0]) * i))
406  instructionParcelsSuccessfullyRead ++;
407  }
408 
409  if (instructionParcelsSuccessfullyRead == nparcels) {
410  cpu->Translate(iwords, nparcels, ic);
411  } else {
412  UI* ui = cpu->GetUI();
413  ui->ShowDebugMessage(cpu, "last part of instruction could not be read");
414  }
415  }
416 
417  cpu->DyntransToBeTranslatedDone(ic);
418 }
419 
420 
421 /*****************************************************************************/
422 
423 
424 #ifdef WITHUNITTESTS
425 
426 #include "ComponentFactory.h"
427 
428 static void Test_RISCV_CPUComponent_Create()
429 {
431  UnitTest::Assert("component was not created?", !cpu.IsNULL());
432 
433  const StateVariable * p = cpu->GetVariable("a0");
434  UnitTest::Assert("cpu has no a0 state variable?", p != NULL);
435 }
436 
437 #if 0
438 static void Test_RISCV_CPUComponent_Disassembly_Basic()
439 {
441  CPUComponent* cpu = RISCV_cpu->AsCPUComponent();
442 
443  vector<string> result;
444  size_t len;
445  unsigned char instruction[sizeof(uint32_t) * 2];
446 
447  // This assumes that the default endianness is little endian...
448  instruction[0] = 0x00;
449  instruction[1] = 0x30;
450  instruction[2] = 0x68;
451  instruction[3] = 0x8c;
452 
453  instruction[4] = 0x01;
454  instruction[5] = 0x23;
455  instruction[6] = 0x34;
456  instruction[7] = 0x45;
457 
458  len = cpu->DisassembleInstruction(0x12345678, sizeof(instruction), instruction, result);
459 
460  UnitTest::Assert("disassembled instruction was wrong length?", len, 8);
461  UnitTest::Assert("disassembly result incomplete?", result.size(), 3);
462  UnitTest::Assert("disassembly result[0]", result[0], "8c683000 45342301");
463  UnitTest::Assert("disassembly result[1]", result[1], "lda");
464  UnitTest::Assert("disassembly result[2]", result[2], "0x45342301,r13");
465 }
466 
467 static GXemul SimpleMachine()
468 {
469  GXemul gxemul;
470  gxemul.GetCommandInterpreter().RunCommand("add mainbus");
471  gxemul.GetCommandInterpreter().RunCommand("add riscv_cpu mainbus0");
472  gxemul.GetCommandInterpreter().RunCommand("add ram mainbus0");
473  gxemul.GetCommandInterpreter().RunCommand("ram0.memoryMappedBase = 0x3fe00000");
474  gxemul.GetCommandInterpreter().RunCommand("ram0.memoryMappedSize = 0x1000");
475  return gxemul;
476 }
477 
478 static void Test_RISCV_CPUComponent_Execute_mov()
479 {
480  GXemul gxemul = SimpleMachine();
481  refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
482  AddressDataBus* bus = cpu->AsAddressDataBus();
483 
484  bus->AddressSelect(0x3fe00048);
485  bus->WriteData((uint32_t)0x5c201e06, LittleEndian); // mov 6,r4
486  bus->AddressSelect(0x3fe0004c);
487  bus->WriteData((uint32_t)0x5c201e06, LittleEndian); // mov 6,r4
488 
489  cpu->SetVariableValue("pc", "0x3fe00048");
490  cpu->SetVariableValue("r4", "0x1234");
491 
493  gxemul.Execute(1);
494 
495  UnitTest::Assert("pc should have increased", cpu->GetVariable("pc")->ToInteger(), 0x3fe0004c);
496  UnitTest::Assert("r4 should have been modified", cpu->GetVariable("r4")->ToInteger(), 6);
497 
498  cpu->SetVariableValue("r4", "0x12345");
499 
501  gxemul.Execute(1);
502 
503  UnitTest::Assert("pc should have increased again", cpu->GetVariable("pc")->ToInteger(), 0x3fe00050);
504  UnitTest::Assert("r4 should have been modified again", cpu->GetVariable("r4")->ToInteger(), 6);
505 }
506 
507 static void Test_RISCV_CPUComponent_Execute_b()
508 {
509  GXemul gxemul = SimpleMachine();
510  refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
511  AddressDataBus* bus = cpu->AsAddressDataBus();
512 
513  bus->AddressSelect(0x3fe00004);
514  bus->WriteData((uint32_t)0x080006c0, LittleEndian); // b 0x3fe006c4
515 
516  cpu->SetVariableValue("pc", "0x3fe00004");
517 
519  gxemul.Execute(1);
520 
521  UnitTest::Assert("pc should have changed", cpu->GetVariable("pc")->ToInteger(), 0x3fe006c4);
522 
523  cpu->SetVariableValue("pc", "0x3fe00004");
524 
526  gxemul.Execute(1);
527 
528  UnitTest::Assert("pc should have changed again", cpu->GetVariable("pc")->ToInteger(), 0x3fe006c4);
529 }
530 
531 static void Test_RISCV_CPUComponent_Execute_lda_with_offset()
532 {
533  GXemul gxemul = SimpleMachine();
534  refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
535  AddressDataBus* bus = cpu->AsAddressDataBus();
536 
537  bus->AddressSelect(0x3fe00010);
538  bus->WriteData((uint32_t)0x8c180f13, LittleEndian); // lda r3, 0xf13
539 
540  cpu->SetVariableValue("pc", "0x3fe00010");
542  gxemul.Execute(1);
543  UnitTest::Assert("lda length", cpu->GetVariable("pc")->ToInteger(), 0x3fe00014);
544  UnitTest::Assert("lda", cpu->GetVariable("r3")->ToInteger(), 0xf13);
545 }
546 
547 static void Test_RISCV_CPUComponent_Execute_lda_with_displacement()
548 {
549  GXemul gxemul = SimpleMachine();
550  refcount_ptr<Component> cpu = gxemul.GetRootComponent()->LookupPath("root.mainbus0.cpu0");
551  AddressDataBus* bus = cpu->AsAddressDataBus();
552 
553  bus->AddressSelect(0x3fe00010);
554  bus->WriteData((uint32_t)0x8cf03000, LittleEndian); // lda
555  bus->AddressSelect(0x3fe00014);
556  bus->WriteData((uint32_t)0x3fe0507c, LittleEndian); // 0x3fe0507c, g14
557 
558  cpu->SetVariableValue("pc", "0x3fe00010");
560  gxemul.Execute(1);
561  UnitTest::Assert("lda length", cpu->GetVariable("pc")->ToInteger(), 0x3fe00018);
562  UnitTest::Assert("lda", cpu->GetVariable("g14")->ToInteger(), 0x3fe0507c);
563 }
564 #endif
565 
567 {
568  UNITTEST(Test_RISCV_CPUComponent_Create);
569 
570 #if 0
571  UNITTEST(Test_RISCV_CPUComponent_Disassembly_Basic);
572 
573  UNITTEST(Test_RISCV_CPUComponent_Execute_mov);
574  UNITTEST(Test_RISCV_CPUComponent_Execute_b);
575  UNITTEST(Test_RISCV_CPUComponent_Execute_lda_with_offset);
576  UNITTEST(Test_RISCV_CPUComponent_Execute_lda_with_displacement);
577 #endif
578 }
579 
580 #endif
N_RISCV_XREGS
#define N_RISCV_XREGS
Definition: RISCV_CPUComponent.h:40
RISCV_CPUComponent::RISCV_CPUComponent
RISCV_CPUComponent()
Constructs a RISCV_CPUComponent.
Definition: RISCV_CPUComponent.cc:38
ComponentFactory::GetCreationArgOverrides
static bool GetCreationArgOverrides(ComponentCreationSettings &settings, const ComponentCreateArgs &createArgs)
Get override arguments for component creation.
Definition: ComponentFactory.cc:151
GXemul::Running
@ Running
Definition: GXemul.h:61
Component::AddVariable
bool AddVariable(const string &name, T *variablePointer)
Adds a state variable of type T to the Component.
Definition: Component.h:563
RISCV_CPUComponent::GetDyntransToBeTranslated
virtual void(*)(CPUDyntransComponent *, DyntransIC *) GetDyntransToBeTranslated()
Definition: RISCV_CPUComponent.h:122
CPUComponent::GetSymbolRegistry
SymbolRegistry & GetSymbolRegistry()
Gets a reference to the CPU's symbol registry.
Definition: CPUComponent.h:63
ComponentFactory.h
GXemul
The main emulator class.
Definition: GXemul.h:55
RISCV_CPUComponent::FunctionTraceReturnImpl
virtual bool FunctionTraceReturnImpl(int64_t &retval)
Definition: RISCV_CPUComponent.cc:144
GXemul::GetCommandInterpreter
CommandInterpreter & GetCommandInterpreter()
Gets a reference to the CommandInterpreter.
Definition: GXemul.cc:623
LittleEndian
@ LittleEndian
Definition: misc.h:159
RISCV_MAX_PARCELS
#define RISCV_MAX_PARCELS
Definition: RISCV_CPUComponent.h:62
StateVariable
StateVariables make up the persistent state of Component objects.
Definition: StateVariable.h:69
CPUComponent::PreRunCheckForComponent
virtual bool PreRunCheckForComponent(GXemul *gxemul)
Checks the state of this component, before starting execution.
Definition: CPUComponent.cc:428
RISCV_CPUComponent::PreRunCheckForComponent
virtual bool PreRunCheckForComponent(GXemul *gxemul)
Checks the state of this component, before starting execution.
Definition: RISCV_CPUComponent.cc:87
RISCV_CPUComponent::FunctionTraceArgumentCount
virtual int FunctionTraceArgumentCount()
Definition: RISCV_CPUComponent.cc:132
CPUComponent::m_frequency
double m_frequency
Definition: CPUComponent.h:194
refcount_ptr< Component >
UNITTESTS
#define UNITTESTS(class)
Helper for unit test case execution.
Definition: UnitTest.h:184
addr
uint32_t addr
Definition: tmp_arm_multi.cc:52
RISCV_CPUComponent.h
Component::GetUI
UI * GetUI()
Gets an UI reference for outputting debug messages during runtime.
Definition: Component.cc:583
CPUDyntransComponent
A base-class for processors Component implementations that use dynamic translation.
Definition: CPUDyntransComponent.h:91
GXemul::GetRootComponent
refcount_ptr< Component > GetRootComponent()
Gets a pointer to the root configuration component.
Definition: GXemul.cc:659
UNITTEST
#define UNITTEST(functionname)
Helper for unit test case execution.
Definition: UnitTest.h:217
UI
Base class for a User Interface.
Definition: UI.h:42
RISCV_CPUComponent::GetDyntransICshift
virtual int GetDyntransICshift() const
Definition: RISCV_CPUComponent.cc:151
UnitTest::Assert
static void Assert(const string &strFailMessage, bool condition)
Asserts that a boolean condition is correct.
Definition: UnitTest.cc:40
AddressDataBus::WriteData
virtual bool WriteData(const uint8_t &data, Endianness endianness=BigEndian)=0
Writes 8-bit data to the currently selected address.
DyntransIC
Definition: CPUDyntransComponent.h:55
CPUComponent::m_pc
uint64_t m_pc
Definition: CPUComponent.h:202
GXemul::SetRunState
void SetRunState(RunState newState)
Sets the RunState.
Definition: GXemul.cc:733
RISCV_CPUComponent::FunctionTraceArgument
virtual int64_t FunctionTraceArgument(int n)
Definition: RISCV_CPUComponent.cc:138
UI::ShowDebugMessage
virtual void ShowDebugMessage(const string &msg)=0
Shows a debug message.
ic
struct arm_instr_call * ic
Definition: tmp_arm_multi.cc:50
GXemul::Execute
void Execute(const int longestTotalRun=100000)
Run the emulation for "a while".
Definition: GXemul.cc:886
SymbolRegistry::LookupAddress
string LookupAddress(uint64_t vaddr, bool allowOffset) const
Looks up an address.
Definition: SymbolRegistry.cc:48
CPUComponent::m_pageSize
int m_pageSize
Definition: CPUComponent.h:199
Component::LookupPath
const refcount_ptr< Component > LookupPath(string path) const
Looks up a path from this Component, and returns a pointer to the found Component,...
Definition: Component.cc:778
ComponentFactory::CreateComponent
static refcount_ptr< Component > CreateComponent(const string &componentNameAndOptionalArgs, GXemul *gxemul=NULL)
Creates a component given a short component name.
Definition: ComponentFactory.cc:87
AddressDataBus::AddressSelect
virtual void AddressSelect(uint64_t address)=0
Place an address on the bus.
DYNTRANS_INSTR_HEAD
#define DYNTRANS_INSTR_HEAD(class)
Definition: CPUDyntransComponent.h:77
DYNTRANS_INSTR
DYNTRANS_INSTR(RISCV_CPUComponent, ToBeTranslated)
Definition: RISCV_CPUComponent.cc:372
RISCV_CPUComponent
A Component representing a RISC-V processor.
Definition: RISCV_CPUComponent.h:77
settings
Definition: settings.cc:57
CPUComponent::m_isBigEndian
bool m_isBigEndian
Definition: CPUComponent.h:210
CommandInterpreter::RunCommand
bool RunCommand(const string &command, bool *pSuccess=NULL)
Runs a command, given as a string.
Definition: CommandInterpreter.cc:958
ComponentCreationSettings
map< string, string > ComponentCreationSettings
Definition: Component.h:46
RISCV_CPUComponent::ShowRegisters
virtual void ShowRegisters(GXemul *gxemul, const vector< string > &arguments) const
Definition: RISCV_CPUComponent.cc:107
RISCV_CPUComponent::GetAttribute
static string GetAttribute(const string &attributeName)
Definition: RISCV_CPUComponent.cc:317
symbol
Definition: symbol.h:37
Component::CheckVariableWrite
virtual bool CheckVariableWrite(StateVariable &var, const string &oldValue)
Checks whether a write to a variable is OK.
Definition: Component.cc:969
GXemul::GetUI
UI * GetUI()
Gets a pointer to the GXemul instance' active UI.
Definition: GXemul.cc:653
RISCV_CPUComponent::PCtoInstructionAddress
virtual uint64_t PCtoInstructionAddress(uint64_t pc)
Convert PC value to instuction address.
Definition: RISCV_CPUComponent.cc:174
GXemul::SingleStepping
@ SingleStepping
Definition: GXemul.h:60
RISCV_CPUComponent::ResetState
virtual void ResetState()
Resets the state variables of this component.
Definition: RISCV_CPUComponent.cc:74
CPUComponent::ReadData
virtual bool ReadData(uint8_t &data, Endianness endianness)
Reads 8-bit data from the currently selected address.
Definition: CPUComponent.cc:504
RISCV_CPUComponent::CheckVariableWrite
virtual bool CheckVariableWrite(StateVariable &var, const string &oldValue)
Checks whether a write to a variable is OK.
Definition: RISCV_CPUComponent.cc:99
RISCV_EXTENSION_I
#define RISCV_EXTENSION_I
Definition: RISCV_CPUComponent.h:66
cpu
Definition: cpu.h:326
Component::AsCPUComponent
virtual CPUComponent * AsCPUComponent()
Returns the component's CPUComponent interface.
Definition: Component.cc:360
AddressDataBus
An interface for implementing components that read/write data via an address bus.
Definition: AddressDataBus.h:45
RISCV_CPUComponent::DisassembleInstruction
virtual size_t DisassembleInstruction(uint64_t vaddr, vector< string > &result)
Disassembles an instruction into readable strings.
Definition: RISCV_CPUComponent.cc:180
Component::GetAttribute
static string GetAttribute(const string &attributeName)
Creates a Component.
Definition: Component.cc:66
CPUComponent::ResetState
virtual void ResetState()
Resets the state variables of this component.
Definition: CPUComponent.cc:82
BigEndian
@ BigEndian
Definition: misc.h:158
RISCV_CPUComponent::VirtualToPhysical
virtual bool VirtualToPhysical(uint64_t vaddr, uint64_t &paddr, bool &writable)
Virtual to physical address translation (MMU).
Definition: RISCV_CPUComponent.cc:165
ComponentCreateArgs
Definition: Component.h:49
CPUComponent::AddressSelect
virtual void AddressSelect(uint64_t address)
Place an address on the bus.
Definition: CPUComponent.cc:498
GXemul.h
RISCV_CPUComponent::Create
static refcount_ptr< Component > Create(const ComponentCreateArgs &args)
Creates a RISCV_CPUComponent.
Definition: RISCV_CPUComponent.cc:57
CPUComponent
A base-class for processors Component implementations.
Definition: CPUComponent.h:47

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