m8820x.h File Reference

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m8820x.h File Reference

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Macros

#define CMMU_IDR   (0x000 / 4) /* CMMU id register */
 
#define CMMU_SCR   (0x004 / 4) /* system command register */
 
#define CMMU_SSR   (0x008 / 4) /* system status register */
 
#define CMMU_SAR   (0x00c / 4) /* system address register */
 
#define CMMU_SCTR   (0x104 / 4) /* system control register */
 
#define CMMU_PFSR   (0x108 / 4) /* P bus fault status register */
 
#define CMMU_PFAR   (0x10c / 4) /* P bus fault address register */
 
#define CMMU_SAPR   (0x200 / 4) /* supervisor area pointer register */
 
#define CMMU_UAPR   (0x204 / 4) /* user area pointer register */
 
#define CMMU_BWP0   (0x400 / 4) /* block ATC writer port 0 */
 
#define CMMU_BWP1   (0x404 / 4) /* block ATC writer port 1 */
 
#define CMMU_BWP2   (0x408 / 4) /* block ATC writer port 2 */
 
#define CMMU_BWP3   (0x40c / 4) /* block ATC writer port 3 */
 
#define CMMU_BWP4   (0x410 / 4) /* block ATC writer port 4 */
 
#define CMMU_BWP5   (0x414 / 4) /* block ATC writer port 5 */
 
#define CMMU_BWP6   (0x418 / 4) /* block ATC writer port 6 */
 
#define CMMU_BWP7   (0x41c / 4) /* block ATC writer port 7 */
 
#define CMMU_BWP(n)   (CMMU_BWP0 + (n))
 
#define CMMU_CDP0   (0x800 / 4) /* cache data port 0 */
 
#define CMMU_CDP1   (0x804 / 4) /* cache data port 1 */
 
#define CMMU_CDP2   (0x808 / 4) /* cache data port 2 */
 
#define CMMU_CDP3   (0x80c / 4) /* cache data port 3 */
 
#define CMMU_CTP0   (0x840 / 4) /* cache tag port 0 */
 
#define CMMU_CTP1   (0x844 / 4) /* cache tag port 1 */
 
#define CMMU_CTP2   (0x848 / 4) /* cache tag port 2 */
 
#define CMMU_CTP3   (0x84c / 4) /* cache tag port 3 */
 
#define CMMU_CSSP0   (0x880 / 4) /* cache set status register */
 
#define CMMU_CSSP(n)   ((0x880 + (n * 0x10)) / 4)
 
#define CMMU_CSSP1   (0x890 / 4) /* cache set status register */
 
#define CMMU_CSSP2   (0x8a0 / 4) /* cache set status register */
 
#define CMMU_CSSP3   (0x8b0 / 4) /* cache set status register */
 
#define CMMU_FLUSH_CACHE_INV_LINE   0x14 /* data cache invalidate */
 
#define CMMU_FLUSH_CACHE_INV_PAGE   0x15
 
#define CMMU_FLUSH_CACHE_INV_SEGMENT   0x16
 
#define CMMU_FLUSH_CACHE_INV_ALL   0x17
 
#define CMMU_FLUSH_CACHE_CB_LINE   0x18 /* data cache copyback */
 
#define CMMU_FLUSH_CACHE_CB_PAGE   0x19
 
#define CMMU_FLUSH_CACHE_CB_SEGMENT   0x1a
 
#define CMMU_FLUSH_CACHE_CB_ALL   0x1b
 
#define CMMU_FLUSH_CACHE_CBI_LINE   0x1c /* copyback and invalidate */
 
#define CMMU_FLUSH_CACHE_CBI_PAGE   0x1d
 
#define CMMU_FLUSH_CACHE_CBI_SEGMENT   0x1e
 
#define CMMU_FLUSH_CACHE_CBI_ALL   0x1f
 
#define CMMU_PROBE_USER   0x20 /* probe user address */
 
#define CMMU_PROBE_SUPER   0x24 /* probe supervisor address */
 
#define CMMU_FLUSH_USER_LINE   0x30 /* flush PATC */
 
#define CMMU_FLUSH_USER_PAGE   0x31
 
#define CMMU_FLUSH_USER_SEGMENT   0x32
 
#define CMMU_FLUSH_USER_ALL   0x33
 
#define CMMU_FLUSH_SUPER_LINE   0x34
 
#define CMMU_FLUSH_SUPER_PAGE   0x35
 
#define CMMU_FLUSH_SUPER_SEGMENT   0x36
 
#define CMMU_FLUSH_SUPER_ALL   0x37
 
#define CMMU_SCTR_PE   0x00008000 /* parity enable */
 
#define CMMU_SCTR_SE   0x00004000 /* snoop enable */
 
#define CMMU_SCTR_PR   0x00002000 /* priority arbitration */
 
#define CMMU_PFSR_FAULT(pfsr)   (((pfsr) >> 16) & 0x07)
 
#define CMMU_PFSR_SUCCESS   0 /* no fault */
 
#define CMMU_PFSR_BERROR   3 /* bus error */
 
#define CMMU_PFSR_SFAULT   4 /* segment fault */
 
#define CMMU_PFSR_PFAULT   5 /* page fault */
 
#define CMMU_PFSR_SUPER   6 /* supervisor violation */
 
#define CMMU_PFSR_WRITE   7 /* writer violation */
 
#define CMMU_CSSP_L5   0x20000000
 
#define CMMU_CSSP_L4   0x10000000
 
#define CMMU_CSSP_L3   0x08000000
 
#define CMMU_CSSP_L2   0x04000000
 
#define CMMU_CSSP_L1   0x02000000
 
#define CMMU_CSSP_L0   0x01000000
 
#define CMMU_CSSP_D3   0x00800000
 
#define CMMU_CSSP_D2   0x00400000
 
#define CMMU_CSSP_D1   0x00200000
 
#define CMMU_CSSP_D0   0x00100000
 
#define CMMU_CSSP_VV(n, v)   (((v) & 0x03) << (12 + 2 * (n)))
 
#define CMMU_VV_EXCLUSIVE   0x00
 
#define CMMU_VV_MODIFIED   0x01
 
#define CMMU_VV_SHARED   0x02
 
#define CMMU_VV_INVALID   0x03
 
#define CMMU_ID(idr)   ((idr) >> 24)
 
#define CMMU_TYPE(idr)   (((idr) >> 21) & 0x07)
 
#define CMMU_VERSION(idr)   (((idr) >> 16) & 0x1f)
 
#define M88200_ID   5
 
#define M88204_ID   6
 
#define CMMU_SSR_CE   0x00008000 /* copyback error */
 
#define CMMU_SSR_BE   0x00004000 /* bus error */
 
#define CMMU_SSR_SO   0x00000100
 
#define CMMU_SSR_M   0x00000010
 
#define CMMU_SSR_U   0x00000008
 
#define CMMU_SSR_PROT   0x00000004
 
#define CMMU_SSR_BH   0x00000002 /* probe BATC hit */
 
#define CMMU_SSR_V   0x00000001
 
#define MC88200_CACHE_SHIFT   4
 
#define MC88200_CACHE_LINE   (1 << MC88200_CACHE_SHIFT)
 
#define BATC8   0xfff7ffb5
 
#define BATC9   0xfffffff5
 
#define BATC8_VA   0xfff00000
 
#define BATC9_VA   0xfff80000
 
#define NBSG   (1 << (PDT_BITS + PG_BITS)) /* segment size */
 
#define INST_CMMU   0x00 /* even number */
 
#define DATA_CMMU   0x01 /* odd number */
 
#define CMMU_MODE(num)   ((num) & 1)
 
#define MAX_CMMUS   8 /* maximum cmmus on the board */
 

Macro Definition Documentation

◆ BATC8

#define BATC8   0xfff7ffb5

Definition at line 177 of file m8820x.h.

◆ BATC8_VA

#define BATC8_VA   0xfff00000

Definition at line 180 of file m8820x.h.

◆ BATC9

#define BATC9   0xfffffff5

Definition at line 178 of file m8820x.h.

◆ BATC9_VA

#define BATC9_VA   0xfff80000

Definition at line 181 of file m8820x.h.

◆ CMMU_BWP

#define CMMU_BWP (   n)    (CMMU_BWP0 + (n))

Definition at line 78 of file m8820x.h.

◆ CMMU_BWP0

#define CMMU_BWP0   (0x400 / 4) /* block ATC writer port 0 */

Definition at line 70 of file m8820x.h.

◆ CMMU_BWP1

#define CMMU_BWP1   (0x404 / 4) /* block ATC writer port 1 */

Definition at line 71 of file m8820x.h.

◆ CMMU_BWP2

#define CMMU_BWP2   (0x408 / 4) /* block ATC writer port 2 */

Definition at line 72 of file m8820x.h.

◆ CMMU_BWP3

#define CMMU_BWP3   (0x40c / 4) /* block ATC writer port 3 */

Definition at line 73 of file m8820x.h.

◆ CMMU_BWP4

#define CMMU_BWP4   (0x410 / 4) /* block ATC writer port 4 */

Definition at line 74 of file m8820x.h.

◆ CMMU_BWP5

#define CMMU_BWP5   (0x414 / 4) /* block ATC writer port 5 */

Definition at line 75 of file m8820x.h.

◆ CMMU_BWP6

#define CMMU_BWP6   (0x418 / 4) /* block ATC writer port 6 */

Definition at line 76 of file m8820x.h.

◆ CMMU_BWP7

#define CMMU_BWP7   (0x41c / 4) /* block ATC writer port 7 */

Definition at line 77 of file m8820x.h.

◆ CMMU_CDP0

#define CMMU_CDP0   (0x800 / 4) /* cache data port 0 */

Definition at line 79 of file m8820x.h.

◆ CMMU_CDP1

#define CMMU_CDP1   (0x804 / 4) /* cache data port 1 */

Definition at line 80 of file m8820x.h.

◆ CMMU_CDP2

#define CMMU_CDP2   (0x808 / 4) /* cache data port 2 */

Definition at line 81 of file m8820x.h.

◆ CMMU_CDP3

#define CMMU_CDP3   (0x80c / 4) /* cache data port 3 */

Definition at line 82 of file m8820x.h.

◆ CMMU_CSSP

#define CMMU_CSSP (   n)    ((0x880 + (n * 0x10)) / 4)

Definition at line 88 of file m8820x.h.

◆ CMMU_CSSP0

#define CMMU_CSSP0   (0x880 / 4) /* cache set status register */

Definition at line 87 of file m8820x.h.

◆ CMMU_CSSP1

#define CMMU_CSSP1   (0x890 / 4) /* cache set status register */

Definition at line 90 of file m8820x.h.

◆ CMMU_CSSP2

#define CMMU_CSSP2   (0x8a0 / 4) /* cache set status register */

Definition at line 91 of file m8820x.h.

◆ CMMU_CSSP3

#define CMMU_CSSP3   (0x8b0 / 4) /* cache set status register */

Definition at line 92 of file m8820x.h.

◆ CMMU_CSSP_D0

#define CMMU_CSSP_D0   0x00100000

Definition at line 142 of file m8820x.h.

◆ CMMU_CSSP_D1

#define CMMU_CSSP_D1   0x00200000

Definition at line 141 of file m8820x.h.

◆ CMMU_CSSP_D2

#define CMMU_CSSP_D2   0x00400000

Definition at line 140 of file m8820x.h.

◆ CMMU_CSSP_D3

#define CMMU_CSSP_D3   0x00800000

Definition at line 139 of file m8820x.h.

◆ CMMU_CSSP_L0

#define CMMU_CSSP_L0   0x01000000

Definition at line 138 of file m8820x.h.

◆ CMMU_CSSP_L1

#define CMMU_CSSP_L1   0x02000000

Definition at line 137 of file m8820x.h.

◆ CMMU_CSSP_L2

#define CMMU_CSSP_L2   0x04000000

Definition at line 136 of file m8820x.h.

◆ CMMU_CSSP_L3

#define CMMU_CSSP_L3   0x08000000

Definition at line 135 of file m8820x.h.

◆ CMMU_CSSP_L4

#define CMMU_CSSP_L4   0x10000000

Definition at line 134 of file m8820x.h.

◆ CMMU_CSSP_L5

#define CMMU_CSSP_L5   0x20000000

Definition at line 133 of file m8820x.h.

◆ CMMU_CSSP_VV

#define CMMU_CSSP_VV (   n,
 
)    (((v) & 0x03) << (12 + 2 * (n)))

Definition at line 143 of file m8820x.h.

◆ CMMU_CTP0

#define CMMU_CTP0   (0x840 / 4) /* cache tag port 0 */

Definition at line 83 of file m8820x.h.

◆ CMMU_CTP1

#define CMMU_CTP1   (0x844 / 4) /* cache tag port 1 */

Definition at line 84 of file m8820x.h.

◆ CMMU_CTP2

#define CMMU_CTP2   (0x848 / 4) /* cache tag port 2 */

Definition at line 85 of file m8820x.h.

◆ CMMU_CTP3

#define CMMU_CTP3   (0x84c / 4) /* cache tag port 3 */

Definition at line 86 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_CB_ALL

#define CMMU_FLUSH_CACHE_CB_ALL   0x1b

Definition at line 102 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_CB_LINE

#define CMMU_FLUSH_CACHE_CB_LINE   0x18 /* data cache copyback */

Definition at line 99 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_CB_PAGE

#define CMMU_FLUSH_CACHE_CB_PAGE   0x19

Definition at line 100 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_CB_SEGMENT

#define CMMU_FLUSH_CACHE_CB_SEGMENT   0x1a

Definition at line 101 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_CBI_ALL

#define CMMU_FLUSH_CACHE_CBI_ALL   0x1f

Definition at line 106 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_CBI_LINE

#define CMMU_FLUSH_CACHE_CBI_LINE   0x1c /* copyback and invalidate */

Definition at line 103 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_CBI_PAGE

#define CMMU_FLUSH_CACHE_CBI_PAGE   0x1d

Definition at line 104 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_CBI_SEGMENT

#define CMMU_FLUSH_CACHE_CBI_SEGMENT   0x1e

Definition at line 105 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_INV_ALL

#define CMMU_FLUSH_CACHE_INV_ALL   0x17

Definition at line 98 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_INV_LINE

#define CMMU_FLUSH_CACHE_INV_LINE   0x14 /* data cache invalidate */

Definition at line 95 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_INV_PAGE

#define CMMU_FLUSH_CACHE_INV_PAGE   0x15

Definition at line 96 of file m8820x.h.

◆ CMMU_FLUSH_CACHE_INV_SEGMENT

#define CMMU_FLUSH_CACHE_INV_SEGMENT   0x16

Definition at line 97 of file m8820x.h.

◆ CMMU_FLUSH_SUPER_ALL

#define CMMU_FLUSH_SUPER_ALL   0x37

Definition at line 116 of file m8820x.h.

◆ CMMU_FLUSH_SUPER_LINE

#define CMMU_FLUSH_SUPER_LINE   0x34

Definition at line 113 of file m8820x.h.

◆ CMMU_FLUSH_SUPER_PAGE

#define CMMU_FLUSH_SUPER_PAGE   0x35

Definition at line 114 of file m8820x.h.

◆ CMMU_FLUSH_SUPER_SEGMENT

#define CMMU_FLUSH_SUPER_SEGMENT   0x36

Definition at line 115 of file m8820x.h.

◆ CMMU_FLUSH_USER_ALL

#define CMMU_FLUSH_USER_ALL   0x33

Definition at line 112 of file m8820x.h.

◆ CMMU_FLUSH_USER_LINE

#define CMMU_FLUSH_USER_LINE   0x30 /* flush PATC */

Definition at line 109 of file m8820x.h.

◆ CMMU_FLUSH_USER_PAGE

#define CMMU_FLUSH_USER_PAGE   0x31

Definition at line 110 of file m8820x.h.

◆ CMMU_FLUSH_USER_SEGMENT

#define CMMU_FLUSH_USER_SEGMENT   0x32

Definition at line 111 of file m8820x.h.

◆ CMMU_ID

#define CMMU_ID (   idr)    ((idr) >> 24)

Definition at line 150 of file m8820x.h.

◆ CMMU_IDR

#define CMMU_IDR   (0x000 / 4) /* CMMU id register */

Definition at line 61 of file m8820x.h.

◆ CMMU_MODE

#define CMMU_MODE (   num)    ((num) & 1)

Definition at line 187 of file m8820x.h.

◆ CMMU_PFAR

#define CMMU_PFAR   (0x10c / 4) /* P bus fault address register */

Definition at line 67 of file m8820x.h.

◆ CMMU_PFSR

#define CMMU_PFSR   (0x108 / 4) /* P bus fault status register */

Definition at line 66 of file m8820x.h.

◆ CMMU_PFSR_BERROR

#define CMMU_PFSR_BERROR   3 /* bus error */

Definition at line 126 of file m8820x.h.

◆ CMMU_PFSR_FAULT

#define CMMU_PFSR_FAULT (   pfsr)    (((pfsr) >> 16) & 0x07)

Definition at line 124 of file m8820x.h.

◆ CMMU_PFSR_PFAULT

#define CMMU_PFSR_PFAULT   5 /* page fault */

Definition at line 128 of file m8820x.h.

◆ CMMU_PFSR_SFAULT

#define CMMU_PFSR_SFAULT   4 /* segment fault */

Definition at line 127 of file m8820x.h.

◆ CMMU_PFSR_SUCCESS

#define CMMU_PFSR_SUCCESS   0 /* no fault */

Definition at line 125 of file m8820x.h.

◆ CMMU_PFSR_SUPER

#define CMMU_PFSR_SUPER   6 /* supervisor violation */

Definition at line 129 of file m8820x.h.

◆ CMMU_PFSR_WRITE

#define CMMU_PFSR_WRITE   7 /* writer violation */

Definition at line 130 of file m8820x.h.

◆ CMMU_PROBE_SUPER

#define CMMU_PROBE_SUPER   0x24 /* probe supervisor address */

Definition at line 108 of file m8820x.h.

◆ CMMU_PROBE_USER

#define CMMU_PROBE_USER   0x20 /* probe user address */

Definition at line 107 of file m8820x.h.

◆ CMMU_SAPR

#define CMMU_SAPR   (0x200 / 4) /* supervisor area pointer register */

Definition at line 68 of file m8820x.h.

◆ CMMU_SAR

#define CMMU_SAR   (0x00c / 4) /* system address register */

Definition at line 64 of file m8820x.h.

◆ CMMU_SCR

#define CMMU_SCR   (0x004 / 4) /* system command register */

Definition at line 62 of file m8820x.h.

◆ CMMU_SCTR

#define CMMU_SCTR   (0x104 / 4) /* system control register */

Definition at line 65 of file m8820x.h.

◆ CMMU_SCTR_PE

#define CMMU_SCTR_PE   0x00008000 /* parity enable */

Definition at line 119 of file m8820x.h.

◆ CMMU_SCTR_PR

#define CMMU_SCTR_PR   0x00002000 /* priority arbitration */

Definition at line 121 of file m8820x.h.

◆ CMMU_SCTR_SE

#define CMMU_SCTR_SE   0x00004000 /* snoop enable */

Definition at line 120 of file m8820x.h.

◆ CMMU_SSR

#define CMMU_SSR   (0x008 / 4) /* system status register */

Definition at line 63 of file m8820x.h.

◆ CMMU_SSR_BE

#define CMMU_SSR_BE   0x00004000 /* bus error */

Definition at line 158 of file m8820x.h.

◆ CMMU_SSR_BH

#define CMMU_SSR_BH   0x00000002 /* probe BATC hit */

Definition at line 163 of file m8820x.h.

◆ CMMU_SSR_CE

#define CMMU_SSR_CE   0x00008000 /* copyback error */

Definition at line 157 of file m8820x.h.

◆ CMMU_SSR_M

#define CMMU_SSR_M   0x00000010

Definition at line 160 of file m8820x.h.

◆ CMMU_SSR_PROT

#define CMMU_SSR_PROT   0x00000004

Definition at line 162 of file m8820x.h.

◆ CMMU_SSR_SO

#define CMMU_SSR_SO   0x00000100

Definition at line 159 of file m8820x.h.

◆ CMMU_SSR_U

#define CMMU_SSR_U   0x00000008

Definition at line 161 of file m8820x.h.

◆ CMMU_SSR_V

#define CMMU_SSR_V   0x00000001

Definition at line 164 of file m8820x.h.

◆ CMMU_TYPE

#define CMMU_TYPE (   idr)    (((idr) >> 21) & 0x07)

Definition at line 151 of file m8820x.h.

◆ CMMU_UAPR

#define CMMU_UAPR   (0x204 / 4) /* user area pointer register */

Definition at line 69 of file m8820x.h.

◆ CMMU_VERSION

#define CMMU_VERSION (   idr)    (((idr) >> 16) & 0x1f)

Definition at line 152 of file m8820x.h.

◆ CMMU_VV_EXCLUSIVE

#define CMMU_VV_EXCLUSIVE   0x00

Definition at line 144 of file m8820x.h.

◆ CMMU_VV_INVALID

#define CMMU_VV_INVALID   0x03

Definition at line 147 of file m8820x.h.

◆ CMMU_VV_MODIFIED

#define CMMU_VV_MODIFIED   0x01

Definition at line 145 of file m8820x.h.

◆ CMMU_VV_SHARED

#define CMMU_VV_SHARED   0x02

Definition at line 146 of file m8820x.h.

◆ DATA_CMMU

#define DATA_CMMU   0x01 /* odd number */

Definition at line 186 of file m8820x.h.

◆ INST_CMMU

#define INST_CMMU   0x00 /* even number */

Definition at line 185 of file m8820x.h.

◆ M88200_ID

#define M88200_ID   5

Definition at line 153 of file m8820x.h.

◆ M88204_ID

#define M88204_ID   6

Definition at line 154 of file m8820x.h.

◆ MAX_CMMUS

#define MAX_CMMUS   8 /* maximum cmmus on the board */

Definition at line 189 of file m8820x.h.

◆ MC88200_CACHE_LINE

#define MC88200_CACHE_LINE   (1 << MC88200_CACHE_SHIFT)

Definition at line 171 of file m8820x.h.

◆ MC88200_CACHE_SHIFT

#define MC88200_CACHE_SHIFT   4

Definition at line 170 of file m8820x.h.

◆ NBSG

#define NBSG   (1 << (PDT_BITS + PG_BITS)) /* segment size */

Definition at line 183 of file m8820x.h.


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