tmp_mips_loadstore_multi.cc Source File

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tmp_mips_loadstore_multi.cc
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1 
2 /* AUTOMATICALLY GENERATED! Do not edit. */
3 
4 #ifdef MODE32
5 X(multi_lw_2_le)
6 {
7  uint32_t *page;
8  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
9  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
10  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
11  uint32_t index0 = addr0 >> 12;
12  page = (uint32_t *) cpu->cd.mips.host_load[index0];
13  if (cpu->delay_slot ||
14  page == NULL || (addr0 & 3) || (addr1 & 3)
15  || ((addr1 ^ addr0) & ~0xfff)) {
16  mips32_loadstore[5](cpu, ic);
17  return;
18  }
19  addr0 = (addr0 >> 2) & 0x3ff;
20  addr1 = (addr1 >> 2) & 0x3ff;
21  r0 = page[addr0];
22  r1 = page[addr1];
23  r0 = LE32_TO_HOST(r0);
24  r1 = LE32_TO_HOST(r1);
25  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
26  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
28  cpu->cd.mips.next_ic += 1;
29 }
30 #else
31 X(multi_lw_2_le)
32 {
33  uint32_t *page;
34  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
35  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
36  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
37  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
38  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
39  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
40  uint32_t x1, x2, x3;
41  struct DYNTRANS_L2_64_TABLE *l2;
42  struct DYNTRANS_L3_64_TABLE *l3;
43  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
44  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
45  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
46  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
47  l3 = l2->l3[x2];
48  page = (uint32_t *) l3->host_load[x3];
49  if (cpu->delay_slot ||
50  page == NULL || (addr0 & 3) || (addr1 & 3)
51  || ((addr1 ^ addr0) & ~0xfff)) {
52  mips_loadstore[5](cpu, ic);
53  return;
54  }
55  addr0 = (addr0 >> 2) & 0x3ff;
56  addr1 = (addr1 >> 2) & 0x3ff;
57  r0 = page[addr0];
58  r1 = page[addr1];
59  r0 = LE32_TO_HOST(r0);
60  r1 = LE32_TO_HOST(r1);
61  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
62  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
64  cpu->cd.mips.next_ic += 1;
65 }
66 #endif
67 
68 #ifdef MODE32
69 X(multi_lw_3_le)
70 {
71  uint32_t *page;
72  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
73  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
74  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
75  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
76  uint32_t index0 = addr0 >> 12;
77  page = (uint32_t *) cpu->cd.mips.host_load[index0];
78  if (cpu->delay_slot ||
79  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
80  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
81  mips32_loadstore[5](cpu, ic);
82  return;
83  }
84  addr0 = (addr0 >> 2) & 0x3ff;
85  addr1 = (addr1 >> 2) & 0x3ff;
86  addr2 = (addr2 >> 2) & 0x3ff;
87  r0 = page[addr0];
88  r1 = page[addr1];
89  r2 = page[addr2];
90  r0 = LE32_TO_HOST(r0);
91  r1 = LE32_TO_HOST(r1);
92  r2 = LE32_TO_HOST(r2);
93  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
94  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
95  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
97  cpu->cd.mips.next_ic += 2;
98 }
99 #else
100 X(multi_lw_3_le)
101 {
102  uint32_t *page;
103  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
104  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
105  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
106  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
107  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
108  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
109  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
110  uint32_t x1, x2, x3;
111  struct DYNTRANS_L2_64_TABLE *l2;
112  struct DYNTRANS_L3_64_TABLE *l3;
113  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
114  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
115  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
116  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
117  l3 = l2->l3[x2];
118  page = (uint32_t *) l3->host_load[x3];
119  if (cpu->delay_slot ||
120  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
121  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
122  mips_loadstore[5](cpu, ic);
123  return;
124  }
125  addr0 = (addr0 >> 2) & 0x3ff;
126  addr1 = (addr1 >> 2) & 0x3ff;
127  addr2 = (addr2 >> 2) & 0x3ff;
128  r0 = page[addr0];
129  r1 = page[addr1];
130  r2 = page[addr2];
131  r0 = LE32_TO_HOST(r0);
132  r1 = LE32_TO_HOST(r1);
133  r2 = LE32_TO_HOST(r2);
134  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
135  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
136  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
137  cpu->n_translated_instrs += 2;
138  cpu->cd.mips.next_ic += 2;
139 }
140 #endif
141 
142 #ifdef MODE32
143 X(multi_lw_4_le)
144 {
145  uint32_t *page;
146  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
147  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
148  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
149  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
150  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
151  uint32_t index0 = addr0 >> 12;
152  page = (uint32_t *) cpu->cd.mips.host_load[index0];
153  if (cpu->delay_slot ||
154  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
155  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
156  mips32_loadstore[5](cpu, ic);
157  return;
158  }
159  addr0 = (addr0 >> 2) & 0x3ff;
160  addr1 = (addr1 >> 2) & 0x3ff;
161  addr2 = (addr2 >> 2) & 0x3ff;
162  addr3 = (addr3 >> 2) & 0x3ff;
163  r0 = page[addr0];
164  r1 = page[addr1];
165  r2 = page[addr2];
166  r3 = page[addr3];
167  r0 = LE32_TO_HOST(r0);
168  r1 = LE32_TO_HOST(r1);
169  r2 = LE32_TO_HOST(r2);
170  r3 = LE32_TO_HOST(r3);
171  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
172  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
173  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
174  reg(ic[3].arg[0]) = (MODE_int_t)(int32_t)r3;
175  cpu->n_translated_instrs += 3;
176  cpu->cd.mips.next_ic += 3;
177 }
178 #else
179 X(multi_lw_4_le)
180 {
181  uint32_t *page;
182  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
183  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
184  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
185  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
186  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
187  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
188  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
189  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
190  uint32_t x1, x2, x3;
191  struct DYNTRANS_L2_64_TABLE *l2;
192  struct DYNTRANS_L3_64_TABLE *l3;
193  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
194  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
195  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
196  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
197  l3 = l2->l3[x2];
198  page = (uint32_t *) l3->host_load[x3];
199  if (cpu->delay_slot ||
200  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
201  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
202  mips_loadstore[5](cpu, ic);
203  return;
204  }
205  addr0 = (addr0 >> 2) & 0x3ff;
206  addr1 = (addr1 >> 2) & 0x3ff;
207  addr2 = (addr2 >> 2) & 0x3ff;
208  addr3 = (addr3 >> 2) & 0x3ff;
209  r0 = page[addr0];
210  r1 = page[addr1];
211  r2 = page[addr2];
212  r3 = page[addr3];
213  r0 = LE32_TO_HOST(r0);
214  r1 = LE32_TO_HOST(r1);
215  r2 = LE32_TO_HOST(r2);
216  r3 = LE32_TO_HOST(r3);
217  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
218  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
219  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
220  reg(ic[3].arg[0]) = (MODE_int_t)(int32_t)r3;
221  cpu->n_translated_instrs += 3;
222  cpu->cd.mips.next_ic += 3;
223 }
224 #endif
225 
226 #ifdef MODE32
227 X(multi_lw_5_le)
228 {
229  uint32_t *page;
230  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3, r4;
231  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
232  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
233  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
234  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
235  MODE_uint_t addr4 = rX + (int32_t)ic[4].arg[2];
236  uint32_t index0 = addr0 >> 12;
237  page = (uint32_t *) cpu->cd.mips.host_load[index0];
238  if (cpu->delay_slot ||
239  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
240  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
241  mips32_loadstore[5](cpu, ic);
242  return;
243  }
244  addr0 = (addr0 >> 2) & 0x3ff;
245  addr1 = (addr1 >> 2) & 0x3ff;
246  addr2 = (addr2 >> 2) & 0x3ff;
247  addr3 = (addr3 >> 2) & 0x3ff;
248  addr4 = (addr4 >> 2) & 0x3ff;
249  r0 = page[addr0];
250  r1 = page[addr1];
251  r2 = page[addr2];
252  r3 = page[addr3];
253  r4 = page[addr4];
254  r0 = LE32_TO_HOST(r0);
255  r1 = LE32_TO_HOST(r1);
256  r2 = LE32_TO_HOST(r2);
257  r3 = LE32_TO_HOST(r3);
258  r4 = LE32_TO_HOST(r4);
259  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
260  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
261  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
262  reg(ic[3].arg[0]) = (MODE_int_t)(int32_t)r3;
263  reg(ic[4].arg[0]) = (MODE_int_t)(int32_t)r4;
264  cpu->n_translated_instrs += 4;
265  cpu->cd.mips.next_ic += 4;
266 }
267 #else
268 X(multi_lw_5_le)
269 {
270  uint32_t *page;
271  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3, r4;
272  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
273  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
274  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
275  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
276  MODE_uint_t addr4 = rX + (int32_t)ic[4].arg[2];
277  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
278  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
279  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
280  uint32_t x1, x2, x3;
281  struct DYNTRANS_L2_64_TABLE *l2;
282  struct DYNTRANS_L3_64_TABLE *l3;
283  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
284  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
285  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
286  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
287  l3 = l2->l3[x2];
288  page = (uint32_t *) l3->host_load[x3];
289  if (cpu->delay_slot ||
290  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
291  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
292  mips_loadstore[5](cpu, ic);
293  return;
294  }
295  addr0 = (addr0 >> 2) & 0x3ff;
296  addr1 = (addr1 >> 2) & 0x3ff;
297  addr2 = (addr2 >> 2) & 0x3ff;
298  addr3 = (addr3 >> 2) & 0x3ff;
299  addr4 = (addr4 >> 2) & 0x3ff;
300  r0 = page[addr0];
301  r1 = page[addr1];
302  r2 = page[addr2];
303  r3 = page[addr3];
304  r4 = page[addr4];
305  r0 = LE32_TO_HOST(r0);
306  r1 = LE32_TO_HOST(r1);
307  r2 = LE32_TO_HOST(r2);
308  r3 = LE32_TO_HOST(r3);
309  r4 = LE32_TO_HOST(r4);
310  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
311  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
312  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
313  reg(ic[3].arg[0]) = (MODE_int_t)(int32_t)r3;
314  reg(ic[4].arg[0]) = (MODE_int_t)(int32_t)r4;
315  cpu->n_translated_instrs += 4;
316  cpu->cd.mips.next_ic += 4;
317 }
318 #endif
319 
320 #ifdef MODE32
321 X(multi_sw_2_le)
322 {
323  uint32_t *page;
324  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
325  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
326  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
327  uint32_t index0 = addr0 >> 12;
328  page = (uint32_t *) cpu->cd.mips.host_store[index0];
329  if (cpu->delay_slot ||
330  page == NULL || (addr0 & 3) || (addr1 & 3)
331  || ((addr1 ^ addr0) & ~0xfff)) {
332  mips32_loadstore[12](cpu, ic);
333  return;
334  }
335  addr0 = (addr0 >> 2) & 0x3ff;
336  addr1 = (addr1 >> 2) & 0x3ff;
337  r0 = reg(ic[0].arg[0]);
338  r1 = reg(ic[1].arg[0]);
339  r0 = LE32_TO_HOST(r0);
340  r1 = LE32_TO_HOST(r1);
341  page[addr0] = r0;
342  page[addr1] = r1;
343  cpu->n_translated_instrs += 1;
344  cpu->cd.mips.next_ic += 1;
345 }
346 #else
347 X(multi_sw_2_le)
348 {
349  uint32_t *page;
350  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
351  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
352  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
353  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
354  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
355  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
356  uint32_t x1, x2, x3;
357  struct DYNTRANS_L2_64_TABLE *l2;
358  struct DYNTRANS_L3_64_TABLE *l3;
359  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
360  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
361  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
362  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
363  l3 = l2->l3[x2];
364  page = (uint32_t *) l3->host_store[x3];
365  if (cpu->delay_slot ||
366  page == NULL || (addr0 & 3) || (addr1 & 3)
367  || ((addr1 ^ addr0) & ~0xfff)) {
368  mips_loadstore[12](cpu, ic);
369  return;
370  }
371  addr0 = (addr0 >> 2) & 0x3ff;
372  addr1 = (addr1 >> 2) & 0x3ff;
373  r0 = reg(ic[0].arg[0]);
374  r1 = reg(ic[1].arg[0]);
375  r0 = LE32_TO_HOST(r0);
376  r1 = LE32_TO_HOST(r1);
377  page[addr0] = r0;
378  page[addr1] = r1;
379  cpu->n_translated_instrs += 1;
380  cpu->cd.mips.next_ic += 1;
381 }
382 #endif
383 
384 #ifdef MODE32
385 X(multi_sw_3_le)
386 {
387  uint32_t *page;
388  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
389  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
390  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
391  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
392  uint32_t index0 = addr0 >> 12;
393  page = (uint32_t *) cpu->cd.mips.host_store[index0];
394  if (cpu->delay_slot ||
395  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
396  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
397  mips32_loadstore[12](cpu, ic);
398  return;
399  }
400  addr0 = (addr0 >> 2) & 0x3ff;
401  addr1 = (addr1 >> 2) & 0x3ff;
402  addr2 = (addr2 >> 2) & 0x3ff;
403  r0 = reg(ic[0].arg[0]);
404  r1 = reg(ic[1].arg[0]);
405  r2 = reg(ic[2].arg[0]);
406  r0 = LE32_TO_HOST(r0);
407  r1 = LE32_TO_HOST(r1);
408  r2 = LE32_TO_HOST(r2);
409  page[addr0] = r0;
410  page[addr1] = r1;
411  page[addr2] = r2;
412  cpu->n_translated_instrs += 2;
413  cpu->cd.mips.next_ic += 2;
414 }
415 #else
416 X(multi_sw_3_le)
417 {
418  uint32_t *page;
419  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
420  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
421  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
422  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
423  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
424  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
425  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
426  uint32_t x1, x2, x3;
427  struct DYNTRANS_L2_64_TABLE *l2;
428  struct DYNTRANS_L3_64_TABLE *l3;
429  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
430  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
431  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
432  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
433  l3 = l2->l3[x2];
434  page = (uint32_t *) l3->host_store[x3];
435  if (cpu->delay_slot ||
436  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
437  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
438  mips_loadstore[12](cpu, ic);
439  return;
440  }
441  addr0 = (addr0 >> 2) & 0x3ff;
442  addr1 = (addr1 >> 2) & 0x3ff;
443  addr2 = (addr2 >> 2) & 0x3ff;
444  r0 = reg(ic[0].arg[0]);
445  r1 = reg(ic[1].arg[0]);
446  r2 = reg(ic[2].arg[0]);
447  r0 = LE32_TO_HOST(r0);
448  r1 = LE32_TO_HOST(r1);
449  r2 = LE32_TO_HOST(r2);
450  page[addr0] = r0;
451  page[addr1] = r1;
452  page[addr2] = r2;
453  cpu->n_translated_instrs += 2;
454  cpu->cd.mips.next_ic += 2;
455 }
456 #endif
457 
458 #ifdef MODE32
459 X(multi_sw_4_le)
460 {
461  uint32_t *page;
462  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
463  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
464  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
465  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
466  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
467  uint32_t index0 = addr0 >> 12;
468  page = (uint32_t *) cpu->cd.mips.host_store[index0];
469  if (cpu->delay_slot ||
470  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
471  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
472  mips32_loadstore[12](cpu, ic);
473  return;
474  }
475  addr0 = (addr0 >> 2) & 0x3ff;
476  addr1 = (addr1 >> 2) & 0x3ff;
477  addr2 = (addr2 >> 2) & 0x3ff;
478  addr3 = (addr3 >> 2) & 0x3ff;
479  r0 = reg(ic[0].arg[0]);
480  r1 = reg(ic[1].arg[0]);
481  r2 = reg(ic[2].arg[0]);
482  r3 = reg(ic[3].arg[0]);
483  r0 = LE32_TO_HOST(r0);
484  r1 = LE32_TO_HOST(r1);
485  r2 = LE32_TO_HOST(r2);
486  r3 = LE32_TO_HOST(r3);
487  page[addr0] = r0;
488  page[addr1] = r1;
489  page[addr2] = r2;
490  page[addr3] = r3;
491  cpu->n_translated_instrs += 3;
492  cpu->cd.mips.next_ic += 3;
493 }
494 #else
495 X(multi_sw_4_le)
496 {
497  uint32_t *page;
498  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
499  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
500  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
501  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
502  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
503  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
504  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
505  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
506  uint32_t x1, x2, x3;
507  struct DYNTRANS_L2_64_TABLE *l2;
508  struct DYNTRANS_L3_64_TABLE *l3;
509  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
510  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
511  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
512  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
513  l3 = l2->l3[x2];
514  page = (uint32_t *) l3->host_store[x3];
515  if (cpu->delay_slot ||
516  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
517  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
518  mips_loadstore[12](cpu, ic);
519  return;
520  }
521  addr0 = (addr0 >> 2) & 0x3ff;
522  addr1 = (addr1 >> 2) & 0x3ff;
523  addr2 = (addr2 >> 2) & 0x3ff;
524  addr3 = (addr3 >> 2) & 0x3ff;
525  r0 = reg(ic[0].arg[0]);
526  r1 = reg(ic[1].arg[0]);
527  r2 = reg(ic[2].arg[0]);
528  r3 = reg(ic[3].arg[0]);
529  r0 = LE32_TO_HOST(r0);
530  r1 = LE32_TO_HOST(r1);
531  r2 = LE32_TO_HOST(r2);
532  r3 = LE32_TO_HOST(r3);
533  page[addr0] = r0;
534  page[addr1] = r1;
535  page[addr2] = r2;
536  page[addr3] = r3;
537  cpu->n_translated_instrs += 3;
538  cpu->cd.mips.next_ic += 3;
539 }
540 #endif
541 
542 #ifdef MODE32
543 X(multi_sw_5_le)
544 {
545  uint32_t *page;
546  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3, r4;
547  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
548  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
549  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
550  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
551  MODE_uint_t addr4 = rX + (int32_t)ic[4].arg[2];
552  uint32_t index0 = addr0 >> 12;
553  page = (uint32_t *) cpu->cd.mips.host_store[index0];
554  if (cpu->delay_slot ||
555  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
556  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
557  mips32_loadstore[12](cpu, ic);
558  return;
559  }
560  addr0 = (addr0 >> 2) & 0x3ff;
561  addr1 = (addr1 >> 2) & 0x3ff;
562  addr2 = (addr2 >> 2) & 0x3ff;
563  addr3 = (addr3 >> 2) & 0x3ff;
564  addr4 = (addr4 >> 2) & 0x3ff;
565  r0 = reg(ic[0].arg[0]);
566  r1 = reg(ic[1].arg[0]);
567  r2 = reg(ic[2].arg[0]);
568  r3 = reg(ic[3].arg[0]);
569  r4 = reg(ic[4].arg[0]);
570  r0 = LE32_TO_HOST(r0);
571  r1 = LE32_TO_HOST(r1);
572  r2 = LE32_TO_HOST(r2);
573  r3 = LE32_TO_HOST(r3);
574  r4 = LE32_TO_HOST(r4);
575  page[addr0] = r0;
576  page[addr1] = r1;
577  page[addr2] = r2;
578  page[addr3] = r3;
579  page[addr4] = r4;
580  cpu->n_translated_instrs += 4;
581  cpu->cd.mips.next_ic += 4;
582 }
583 #else
584 X(multi_sw_5_le)
585 {
586  uint32_t *page;
587  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3, r4;
588  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
589  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
590  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
591  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
592  MODE_uint_t addr4 = rX + (int32_t)ic[4].arg[2];
593  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
594  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
595  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
596  uint32_t x1, x2, x3;
597  struct DYNTRANS_L2_64_TABLE *l2;
598  struct DYNTRANS_L3_64_TABLE *l3;
599  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
600  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
601  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
602  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
603  l3 = l2->l3[x2];
604  page = (uint32_t *) l3->host_store[x3];
605  if (cpu->delay_slot ||
606  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
607  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
608  mips_loadstore[12](cpu, ic);
609  return;
610  }
611  addr0 = (addr0 >> 2) & 0x3ff;
612  addr1 = (addr1 >> 2) & 0x3ff;
613  addr2 = (addr2 >> 2) & 0x3ff;
614  addr3 = (addr3 >> 2) & 0x3ff;
615  addr4 = (addr4 >> 2) & 0x3ff;
616  r0 = reg(ic[0].arg[0]);
617  r1 = reg(ic[1].arg[0]);
618  r2 = reg(ic[2].arg[0]);
619  r3 = reg(ic[3].arg[0]);
620  r4 = reg(ic[4].arg[0]);
621  r0 = LE32_TO_HOST(r0);
622  r1 = LE32_TO_HOST(r1);
623  r2 = LE32_TO_HOST(r2);
624  r3 = LE32_TO_HOST(r3);
625  r4 = LE32_TO_HOST(r4);
626  page[addr0] = r0;
627  page[addr1] = r1;
628  page[addr2] = r2;
629  page[addr3] = r3;
630  page[addr4] = r4;
631  cpu->n_translated_instrs += 4;
632  cpu->cd.mips.next_ic += 4;
633 }
634 #endif
635 
636 #ifdef MODE32
637 X(multi_lw_2_be)
638 {
639  uint32_t *page;
640  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
641  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
642  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
643  uint32_t index0 = addr0 >> 12;
644  page = (uint32_t *) cpu->cd.mips.host_load[index0];
645  if (cpu->delay_slot ||
646  page == NULL || (addr0 & 3) || (addr1 & 3)
647  || ((addr1 ^ addr0) & ~0xfff)) {
648  mips32_loadstore[21](cpu, ic);
649  return;
650  }
651  addr0 = (addr0 >> 2) & 0x3ff;
652  addr1 = (addr1 >> 2) & 0x3ff;
653  r0 = page[addr0];
654  r1 = page[addr1];
655  r0 = BE32_TO_HOST(r0);
656  r1 = BE32_TO_HOST(r1);
657  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
658  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
659  cpu->n_translated_instrs += 1;
660  cpu->cd.mips.next_ic += 1;
661 }
662 #else
663 X(multi_lw_2_be)
664 {
665  uint32_t *page;
666  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
667  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
668  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
669  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
670  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
671  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
672  uint32_t x1, x2, x3;
673  struct DYNTRANS_L2_64_TABLE *l2;
674  struct DYNTRANS_L3_64_TABLE *l3;
675  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
676  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
677  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
678  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
679  l3 = l2->l3[x2];
680  page = (uint32_t *) l3->host_load[x3];
681  if (cpu->delay_slot ||
682  page == NULL || (addr0 & 3) || (addr1 & 3)
683  || ((addr1 ^ addr0) & ~0xfff)) {
684  mips_loadstore[21](cpu, ic);
685  return;
686  }
687  addr0 = (addr0 >> 2) & 0x3ff;
688  addr1 = (addr1 >> 2) & 0x3ff;
689  r0 = page[addr0];
690  r1 = page[addr1];
691  r0 = BE32_TO_HOST(r0);
692  r1 = BE32_TO_HOST(r1);
693  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
694  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
695  cpu->n_translated_instrs += 1;
696  cpu->cd.mips.next_ic += 1;
697 }
698 #endif
699 
700 #ifdef MODE32
701 X(multi_lw_3_be)
702 {
703  uint32_t *page;
704  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
705  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
706  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
707  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
708  uint32_t index0 = addr0 >> 12;
709  page = (uint32_t *) cpu->cd.mips.host_load[index0];
710  if (cpu->delay_slot ||
711  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
712  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
713  mips32_loadstore[21](cpu, ic);
714  return;
715  }
716  addr0 = (addr0 >> 2) & 0x3ff;
717  addr1 = (addr1 >> 2) & 0x3ff;
718  addr2 = (addr2 >> 2) & 0x3ff;
719  r0 = page[addr0];
720  r1 = page[addr1];
721  r2 = page[addr2];
722  r0 = BE32_TO_HOST(r0);
723  r1 = BE32_TO_HOST(r1);
724  r2 = BE32_TO_HOST(r2);
725  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
726  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
727  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
728  cpu->n_translated_instrs += 2;
729  cpu->cd.mips.next_ic += 2;
730 }
731 #else
732 X(multi_lw_3_be)
733 {
734  uint32_t *page;
735  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
736  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
737  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
738  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
739  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
740  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
741  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
742  uint32_t x1, x2, x3;
743  struct DYNTRANS_L2_64_TABLE *l2;
744  struct DYNTRANS_L3_64_TABLE *l3;
745  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
746  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
747  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
748  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
749  l3 = l2->l3[x2];
750  page = (uint32_t *) l3->host_load[x3];
751  if (cpu->delay_slot ||
752  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
753  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
754  mips_loadstore[21](cpu, ic);
755  return;
756  }
757  addr0 = (addr0 >> 2) & 0x3ff;
758  addr1 = (addr1 >> 2) & 0x3ff;
759  addr2 = (addr2 >> 2) & 0x3ff;
760  r0 = page[addr0];
761  r1 = page[addr1];
762  r2 = page[addr2];
763  r0 = BE32_TO_HOST(r0);
764  r1 = BE32_TO_HOST(r1);
765  r2 = BE32_TO_HOST(r2);
766  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
767  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
768  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
769  cpu->n_translated_instrs += 2;
770  cpu->cd.mips.next_ic += 2;
771 }
772 #endif
773 
774 #ifdef MODE32
775 X(multi_lw_4_be)
776 {
777  uint32_t *page;
778  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
779  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
780  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
781  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
782  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
783  uint32_t index0 = addr0 >> 12;
784  page = (uint32_t *) cpu->cd.mips.host_load[index0];
785  if (cpu->delay_slot ||
786  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
787  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
788  mips32_loadstore[21](cpu, ic);
789  return;
790  }
791  addr0 = (addr0 >> 2) & 0x3ff;
792  addr1 = (addr1 >> 2) & 0x3ff;
793  addr2 = (addr2 >> 2) & 0x3ff;
794  addr3 = (addr3 >> 2) & 0x3ff;
795  r0 = page[addr0];
796  r1 = page[addr1];
797  r2 = page[addr2];
798  r3 = page[addr3];
799  r0 = BE32_TO_HOST(r0);
800  r1 = BE32_TO_HOST(r1);
801  r2 = BE32_TO_HOST(r2);
802  r3 = BE32_TO_HOST(r3);
803  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
804  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
805  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
806  reg(ic[3].arg[0]) = (MODE_int_t)(int32_t)r3;
807  cpu->n_translated_instrs += 3;
808  cpu->cd.mips.next_ic += 3;
809 }
810 #else
811 X(multi_lw_4_be)
812 {
813  uint32_t *page;
814  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
815  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
816  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
817  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
818  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
819  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
820  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
821  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
822  uint32_t x1, x2, x3;
823  struct DYNTRANS_L2_64_TABLE *l2;
824  struct DYNTRANS_L3_64_TABLE *l3;
825  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
826  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
827  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
828  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
829  l3 = l2->l3[x2];
830  page = (uint32_t *) l3->host_load[x3];
831  if (cpu->delay_slot ||
832  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
833  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
834  mips_loadstore[21](cpu, ic);
835  return;
836  }
837  addr0 = (addr0 >> 2) & 0x3ff;
838  addr1 = (addr1 >> 2) & 0x3ff;
839  addr2 = (addr2 >> 2) & 0x3ff;
840  addr3 = (addr3 >> 2) & 0x3ff;
841  r0 = page[addr0];
842  r1 = page[addr1];
843  r2 = page[addr2];
844  r3 = page[addr3];
845  r0 = BE32_TO_HOST(r0);
846  r1 = BE32_TO_HOST(r1);
847  r2 = BE32_TO_HOST(r2);
848  r3 = BE32_TO_HOST(r3);
849  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
850  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
851  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
852  reg(ic[3].arg[0]) = (MODE_int_t)(int32_t)r3;
853  cpu->n_translated_instrs += 3;
854  cpu->cd.mips.next_ic += 3;
855 }
856 #endif
857 
858 #ifdef MODE32
859 X(multi_lw_5_be)
860 {
861  uint32_t *page;
862  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3, r4;
863  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
864  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
865  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
866  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
867  MODE_uint_t addr4 = rX + (int32_t)ic[4].arg[2];
868  uint32_t index0 = addr0 >> 12;
869  page = (uint32_t *) cpu->cd.mips.host_load[index0];
870  if (cpu->delay_slot ||
871  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
872  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
873  mips32_loadstore[21](cpu, ic);
874  return;
875  }
876  addr0 = (addr0 >> 2) & 0x3ff;
877  addr1 = (addr1 >> 2) & 0x3ff;
878  addr2 = (addr2 >> 2) & 0x3ff;
879  addr3 = (addr3 >> 2) & 0x3ff;
880  addr4 = (addr4 >> 2) & 0x3ff;
881  r0 = page[addr0];
882  r1 = page[addr1];
883  r2 = page[addr2];
884  r3 = page[addr3];
885  r4 = page[addr4];
886  r0 = BE32_TO_HOST(r0);
887  r1 = BE32_TO_HOST(r1);
888  r2 = BE32_TO_HOST(r2);
889  r3 = BE32_TO_HOST(r3);
890  r4 = BE32_TO_HOST(r4);
891  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
892  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
893  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
894  reg(ic[3].arg[0]) = (MODE_int_t)(int32_t)r3;
895  reg(ic[4].arg[0]) = (MODE_int_t)(int32_t)r4;
896  cpu->n_translated_instrs += 4;
897  cpu->cd.mips.next_ic += 4;
898 }
899 #else
900 X(multi_lw_5_be)
901 {
902  uint32_t *page;
903  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3, r4;
904  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
905  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
906  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
907  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
908  MODE_uint_t addr4 = rX + (int32_t)ic[4].arg[2];
909  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
910  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
911  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
912  uint32_t x1, x2, x3;
913  struct DYNTRANS_L2_64_TABLE *l2;
914  struct DYNTRANS_L3_64_TABLE *l3;
915  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
916  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
917  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
918  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
919  l3 = l2->l3[x2];
920  page = (uint32_t *) l3->host_load[x3];
921  if (cpu->delay_slot ||
922  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
923  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
924  mips_loadstore[21](cpu, ic);
925  return;
926  }
927  addr0 = (addr0 >> 2) & 0x3ff;
928  addr1 = (addr1 >> 2) & 0x3ff;
929  addr2 = (addr2 >> 2) & 0x3ff;
930  addr3 = (addr3 >> 2) & 0x3ff;
931  addr4 = (addr4 >> 2) & 0x3ff;
932  r0 = page[addr0];
933  r1 = page[addr1];
934  r2 = page[addr2];
935  r3 = page[addr3];
936  r4 = page[addr4];
937  r0 = BE32_TO_HOST(r0);
938  r1 = BE32_TO_HOST(r1);
939  r2 = BE32_TO_HOST(r2);
940  r3 = BE32_TO_HOST(r3);
941  r4 = BE32_TO_HOST(r4);
942  reg(ic[0].arg[0]) = (MODE_int_t)(int32_t)r0;
943  reg(ic[1].arg[0]) = (MODE_int_t)(int32_t)r1;
944  reg(ic[2].arg[0]) = (MODE_int_t)(int32_t)r2;
945  reg(ic[3].arg[0]) = (MODE_int_t)(int32_t)r3;
946  reg(ic[4].arg[0]) = (MODE_int_t)(int32_t)r4;
947  cpu->n_translated_instrs += 4;
948  cpu->cd.mips.next_ic += 4;
949 }
950 #endif
951 
952 #ifdef MODE32
953 X(multi_sw_2_be)
954 {
955  uint32_t *page;
956  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
957  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
958  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
959  uint32_t index0 = addr0 >> 12;
960  page = (uint32_t *) cpu->cd.mips.host_store[index0];
961  if (cpu->delay_slot ||
962  page == NULL || (addr0 & 3) || (addr1 & 3)
963  || ((addr1 ^ addr0) & ~0xfff)) {
964  mips32_loadstore[28](cpu, ic);
965  return;
966  }
967  addr0 = (addr0 >> 2) & 0x3ff;
968  addr1 = (addr1 >> 2) & 0x3ff;
969  r0 = reg(ic[0].arg[0]);
970  r1 = reg(ic[1].arg[0]);
971  r0 = BE32_TO_HOST(r0);
972  r1 = BE32_TO_HOST(r1);
973  page[addr0] = r0;
974  page[addr1] = r1;
975  cpu->n_translated_instrs += 1;
976  cpu->cd.mips.next_ic += 1;
977 }
978 #else
979 X(multi_sw_2_be)
980 {
981  uint32_t *page;
982  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
983  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
984  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
985  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
986  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
987  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
988  uint32_t x1, x2, x3;
989  struct DYNTRANS_L2_64_TABLE *l2;
990  struct DYNTRANS_L3_64_TABLE *l3;
991  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
992  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
993  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
994  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
995  l3 = l2->l3[x2];
996  page = (uint32_t *) l3->host_store[x3];
997  if (cpu->delay_slot ||
998  page == NULL || (addr0 & 3) || (addr1 & 3)
999  || ((addr1 ^ addr0) & ~0xfff)) {
1000  mips_loadstore[28](cpu, ic);
1001  return;
1002  }
1003  addr0 = (addr0 >> 2) & 0x3ff;
1004  addr1 = (addr1 >> 2) & 0x3ff;
1005  r0 = reg(ic[0].arg[0]);
1006  r1 = reg(ic[1].arg[0]);
1007  r0 = BE32_TO_HOST(r0);
1008  r1 = BE32_TO_HOST(r1);
1009  page[addr0] = r0;
1010  page[addr1] = r1;
1011  cpu->n_translated_instrs += 1;
1012  cpu->cd.mips.next_ic += 1;
1013 }
1014 #endif
1015 
1016 #ifdef MODE32
1017 X(multi_sw_3_be)
1018 {
1019  uint32_t *page;
1020  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
1021  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
1022  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
1023  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
1024  uint32_t index0 = addr0 >> 12;
1025  page = (uint32_t *) cpu->cd.mips.host_store[index0];
1026  if (cpu->delay_slot ||
1027  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
1028  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
1029  mips32_loadstore[28](cpu, ic);
1030  return;
1031  }
1032  addr0 = (addr0 >> 2) & 0x3ff;
1033  addr1 = (addr1 >> 2) & 0x3ff;
1034  addr2 = (addr2 >> 2) & 0x3ff;
1035  r0 = reg(ic[0].arg[0]);
1036  r1 = reg(ic[1].arg[0]);
1037  r2 = reg(ic[2].arg[0]);
1038  r0 = BE32_TO_HOST(r0);
1039  r1 = BE32_TO_HOST(r1);
1040  r2 = BE32_TO_HOST(r2);
1041  page[addr0] = r0;
1042  page[addr1] = r1;
1043  page[addr2] = r2;
1044  cpu->n_translated_instrs += 2;
1045  cpu->cd.mips.next_ic += 2;
1046 }
1047 #else
1048 X(multi_sw_3_be)
1049 {
1050  uint32_t *page;
1051  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
1052  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
1053  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
1054  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
1055  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
1056  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
1057  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
1058  uint32_t x1, x2, x3;
1059  struct DYNTRANS_L2_64_TABLE *l2;
1060  struct DYNTRANS_L3_64_TABLE *l3;
1061  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
1062  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
1063  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
1064  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
1065  l3 = l2->l3[x2];
1066  page = (uint32_t *) l3->host_store[x3];
1067  if (cpu->delay_slot ||
1068  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
1069  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
1070  mips_loadstore[28](cpu, ic);
1071  return;
1072  }
1073  addr0 = (addr0 >> 2) & 0x3ff;
1074  addr1 = (addr1 >> 2) & 0x3ff;
1075  addr2 = (addr2 >> 2) & 0x3ff;
1076  r0 = reg(ic[0].arg[0]);
1077  r1 = reg(ic[1].arg[0]);
1078  r2 = reg(ic[2].arg[0]);
1079  r0 = BE32_TO_HOST(r0);
1080  r1 = BE32_TO_HOST(r1);
1081  r2 = BE32_TO_HOST(r2);
1082  page[addr0] = r0;
1083  page[addr1] = r1;
1084  page[addr2] = r2;
1085  cpu->n_translated_instrs += 2;
1086  cpu->cd.mips.next_ic += 2;
1087 }
1088 #endif
1089 
1090 #ifdef MODE32
1091 X(multi_sw_4_be)
1092 {
1093  uint32_t *page;
1094  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
1095  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
1096  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
1097  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
1098  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
1099  uint32_t index0 = addr0 >> 12;
1100  page = (uint32_t *) cpu->cd.mips.host_store[index0];
1101  if (cpu->delay_slot ||
1102  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
1103  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
1104  mips32_loadstore[28](cpu, ic);
1105  return;
1106  }
1107  addr0 = (addr0 >> 2) & 0x3ff;
1108  addr1 = (addr1 >> 2) & 0x3ff;
1109  addr2 = (addr2 >> 2) & 0x3ff;
1110  addr3 = (addr3 >> 2) & 0x3ff;
1111  r0 = reg(ic[0].arg[0]);
1112  r1 = reg(ic[1].arg[0]);
1113  r2 = reg(ic[2].arg[0]);
1114  r3 = reg(ic[3].arg[0]);
1115  r0 = BE32_TO_HOST(r0);
1116  r1 = BE32_TO_HOST(r1);
1117  r2 = BE32_TO_HOST(r2);
1118  r3 = BE32_TO_HOST(r3);
1119  page[addr0] = r0;
1120  page[addr1] = r1;
1121  page[addr2] = r2;
1122  page[addr3] = r3;
1123  cpu->n_translated_instrs += 3;
1124  cpu->cd.mips.next_ic += 3;
1125 }
1126 #else
1127 X(multi_sw_4_be)
1128 {
1129  uint32_t *page;
1130  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
1131  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
1132  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
1133  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
1134  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
1135  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
1136  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
1137  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
1138  uint32_t x1, x2, x3;
1139  struct DYNTRANS_L2_64_TABLE *l2;
1140  struct DYNTRANS_L3_64_TABLE *l3;
1141  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
1142  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
1143  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
1144  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
1145  l3 = l2->l3[x2];
1146  page = (uint32_t *) l3->host_store[x3];
1147  if (cpu->delay_slot ||
1148  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
1149  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
1150  mips_loadstore[28](cpu, ic);
1151  return;
1152  }
1153  addr0 = (addr0 >> 2) & 0x3ff;
1154  addr1 = (addr1 >> 2) & 0x3ff;
1155  addr2 = (addr2 >> 2) & 0x3ff;
1156  addr3 = (addr3 >> 2) & 0x3ff;
1157  r0 = reg(ic[0].arg[0]);
1158  r1 = reg(ic[1].arg[0]);
1159  r2 = reg(ic[2].arg[0]);
1160  r3 = reg(ic[3].arg[0]);
1161  r0 = BE32_TO_HOST(r0);
1162  r1 = BE32_TO_HOST(r1);
1163  r2 = BE32_TO_HOST(r2);
1164  r3 = BE32_TO_HOST(r3);
1165  page[addr0] = r0;
1166  page[addr1] = r1;
1167  page[addr2] = r2;
1168  page[addr3] = r3;
1169  cpu->n_translated_instrs += 3;
1170  cpu->cd.mips.next_ic += 3;
1171 }
1172 #endif
1173 
1174 #ifdef MODE32
1175 X(multi_sw_5_be)
1176 {
1177  uint32_t *page;
1178  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3, r4;
1179  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
1180  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
1181  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
1182  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
1183  MODE_uint_t addr4 = rX + (int32_t)ic[4].arg[2];
1184  uint32_t index0 = addr0 >> 12;
1185  page = (uint32_t *) cpu->cd.mips.host_store[index0];
1186  if (cpu->delay_slot ||
1187  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
1188  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
1189  mips32_loadstore[28](cpu, ic);
1190  return;
1191  }
1192  addr0 = (addr0 >> 2) & 0x3ff;
1193  addr1 = (addr1 >> 2) & 0x3ff;
1194  addr2 = (addr2 >> 2) & 0x3ff;
1195  addr3 = (addr3 >> 2) & 0x3ff;
1196  addr4 = (addr4 >> 2) & 0x3ff;
1197  r0 = reg(ic[0].arg[0]);
1198  r1 = reg(ic[1].arg[0]);
1199  r2 = reg(ic[2].arg[0]);
1200  r3 = reg(ic[3].arg[0]);
1201  r4 = reg(ic[4].arg[0]);
1202  r0 = BE32_TO_HOST(r0);
1203  r1 = BE32_TO_HOST(r1);
1204  r2 = BE32_TO_HOST(r2);
1205  r3 = BE32_TO_HOST(r3);
1206  r4 = BE32_TO_HOST(r4);
1207  page[addr0] = r0;
1208  page[addr1] = r1;
1209  page[addr2] = r2;
1210  page[addr3] = r3;
1211  page[addr4] = r4;
1212  cpu->n_translated_instrs += 4;
1213  cpu->cd.mips.next_ic += 4;
1214 }
1215 #else
1216 X(multi_sw_5_be)
1217 {
1218  uint32_t *page;
1219  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3, r4;
1220  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
1221  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
1222  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
1223  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
1224  MODE_uint_t addr4 = rX + (int32_t)ic[4].arg[2];
1225  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
1226  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
1227  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
1228  uint32_t x1, x2, x3;
1229  struct DYNTRANS_L2_64_TABLE *l2;
1230  struct DYNTRANS_L3_64_TABLE *l3;
1231  x1 = (addr0 >> (64-DYNTRANS_L1N)) & mask1;
1232  x2 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
1233  x3 = (addr0 >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
1234  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
1235  l3 = l2->l3[x2];
1236  page = (uint32_t *) l3->host_store[x3];
1237  if (cpu->delay_slot ||
1238  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
1239  || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
1240  mips_loadstore[28](cpu, ic);
1241  return;
1242  }
1243  addr0 = (addr0 >> 2) & 0x3ff;
1244  addr1 = (addr1 >> 2) & 0x3ff;
1245  addr2 = (addr2 >> 2) & 0x3ff;
1246  addr3 = (addr3 >> 2) & 0x3ff;
1247  addr4 = (addr4 >> 2) & 0x3ff;
1248  r0 = reg(ic[0].arg[0]);
1249  r1 = reg(ic[1].arg[0]);
1250  r2 = reg(ic[2].arg[0]);
1251  r3 = reg(ic[3].arg[0]);
1252  r4 = reg(ic[4].arg[0]);
1253  r0 = BE32_TO_HOST(r0);
1254  r1 = BE32_TO_HOST(r1);
1255  r2 = BE32_TO_HOST(r2);
1256  r3 = BE32_TO_HOST(r3);
1257  r4 = BE32_TO_HOST(r4);
1258  page[addr0] = r0;
1259  page[addr1] = r1;
1260  page[addr2] = r2;
1261  page[addr3] = r3;
1262  page[addr4] = r4;
1263  cpu->n_translated_instrs += 4;
1264  cpu->cd.mips.next_ic += 4;
1265 }
1266 #endif
1267 
X
X(multi_lw_2_le)
Definition: tmp_mips_loadstore_multi.cc:31
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Definition: tmp_mips_loadstore.cc:713
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Definition: cpu.h:430
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Definition: tmp_arm_multi.cc:56
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#define DYNTRANS_L1N
Definition: cpu.h:222
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Definition: misc.h:180
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Definition: cpu.h:446
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Definition: misc.h:181
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Definition: tmp_arm_multi.cc:54
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Definition: tmp_arm_multi.cc:50
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Definition: tmp_alpha_tail.cc:53
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Definition: tmp_alpha_head.cc:16
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Definition: tmp_alpha_tail.cc:54

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