11 uint32_t index0 = addr0 >> 12;
14 page == NULL || (addr0 & 3) || (addr1 & 3)
15 || ((addr1 ^ addr0) & ~0xfff)) {
16 mips32_loadstore[5](
cpu,
ic);
19 addr0 = (addr0 >> 2) & 0x3ff;
20 addr1 = (addr1 >> 2) & 0x3ff;
46 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
48 page = (uint32_t *) l3->host_load[x3];
50 page == NULL || (addr0 & 3) || (addr1 & 3)
51 || ((addr1 ^ addr0) & ~0xfff)) {
55 addr0 = (addr0 >> 2) & 0x3ff;
56 addr1 = (addr1 >> 2) & 0x3ff;
76 uint32_t index0 = addr0 >> 12;
79 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
80 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
81 mips32_loadstore[5](
cpu,
ic);
84 addr0 = (addr0 >> 2) & 0x3ff;
85 addr1 = (addr1 >> 2) & 0x3ff;
86 addr2 = (addr2 >> 2) & 0x3ff;
116 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
118 page = (uint32_t *) l3->host_load[x3];
120 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
121 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
125 addr0 = (addr0 >> 2) & 0x3ff;
126 addr1 = (addr1 >> 2) & 0x3ff;
127 addr2 = (addr2 >> 2) & 0x3ff;
151 uint32_t index0 = addr0 >> 12;
154 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
155 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
156 mips32_loadstore[5](
cpu,
ic);
159 addr0 = (addr0 >> 2) & 0x3ff;
160 addr1 = (addr1 >> 2) & 0x3ff;
161 addr2 = (addr2 >> 2) & 0x3ff;
162 addr3 = (addr3 >> 2) & 0x3ff;
196 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
198 page = (uint32_t *) l3->host_load[x3];
200 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
201 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
205 addr0 = (addr0 >> 2) & 0x3ff;
206 addr1 = (addr1 >> 2) & 0x3ff;
207 addr2 = (addr2 >> 2) & 0x3ff;
208 addr3 = (addr3 >> 2) & 0x3ff;
236 uint32_t index0 = addr0 >> 12;
239 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
240 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
241 mips32_loadstore[5](
cpu,
ic);
244 addr0 = (addr0 >> 2) & 0x3ff;
245 addr1 = (addr1 >> 2) & 0x3ff;
246 addr2 = (addr2 >> 2) & 0x3ff;
247 addr3 = (addr3 >> 2) & 0x3ff;
248 addr4 = (addr4 >> 2) & 0x3ff;
286 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
288 page = (uint32_t *) l3->host_load[x3];
290 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
291 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
295 addr0 = (addr0 >> 2) & 0x3ff;
296 addr1 = (addr1 >> 2) & 0x3ff;
297 addr2 = (addr2 >> 2) & 0x3ff;
298 addr3 = (addr3 >> 2) & 0x3ff;
299 addr4 = (addr4 >> 2) & 0x3ff;
327 uint32_t index0 = addr0 >> 12;
330 page == NULL || (addr0 & 3) || (addr1 & 3)
331 || ((addr1 ^ addr0) & ~0xfff)) {
332 mips32_loadstore[12](
cpu,
ic);
335 addr0 = (addr0 >> 2) & 0x3ff;
336 addr1 = (addr1 >> 2) & 0x3ff;
337 r0 =
reg(
ic[0].arg[0]);
338 r1 =
reg(
ic[1].arg[0]);
362 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
364 page = (uint32_t *) l3->host_store[x3];
366 page == NULL || (addr0 & 3) || (addr1 & 3)
367 || ((addr1 ^ addr0) & ~0xfff)) {
371 addr0 = (addr0 >> 2) & 0x3ff;
372 addr1 = (addr1 >> 2) & 0x3ff;
373 r0 =
reg(
ic[0].arg[0]);
374 r1 =
reg(
ic[1].arg[0]);
392 uint32_t index0 = addr0 >> 12;
395 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
396 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
397 mips32_loadstore[12](
cpu,
ic);
400 addr0 = (addr0 >> 2) & 0x3ff;
401 addr1 = (addr1 >> 2) & 0x3ff;
402 addr2 = (addr2 >> 2) & 0x3ff;
403 r0 =
reg(
ic[0].arg[0]);
404 r1 =
reg(
ic[1].arg[0]);
405 r2 =
reg(
ic[2].arg[0]);
432 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
434 page = (uint32_t *) l3->host_store[x3];
436 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
437 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
441 addr0 = (addr0 >> 2) & 0x3ff;
442 addr1 = (addr1 >> 2) & 0x3ff;
443 addr2 = (addr2 >> 2) & 0x3ff;
444 r0 =
reg(
ic[0].arg[0]);
445 r1 =
reg(
ic[1].arg[0]);
446 r2 =
reg(
ic[2].arg[0]);
467 uint32_t index0 = addr0 >> 12;
470 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
471 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
472 mips32_loadstore[12](
cpu,
ic);
475 addr0 = (addr0 >> 2) & 0x3ff;
476 addr1 = (addr1 >> 2) & 0x3ff;
477 addr2 = (addr2 >> 2) & 0x3ff;
478 addr3 = (addr3 >> 2) & 0x3ff;
479 r0 =
reg(
ic[0].arg[0]);
480 r1 =
reg(
ic[1].arg[0]);
481 r2 =
reg(
ic[2].arg[0]);
482 r3 =
reg(
ic[3].arg[0]);
512 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
514 page = (uint32_t *) l3->host_store[x3];
516 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
517 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
521 addr0 = (addr0 >> 2) & 0x3ff;
522 addr1 = (addr1 >> 2) & 0x3ff;
523 addr2 = (addr2 >> 2) & 0x3ff;
524 addr3 = (addr3 >> 2) & 0x3ff;
525 r0 =
reg(
ic[0].arg[0]);
526 r1 =
reg(
ic[1].arg[0]);
527 r2 =
reg(
ic[2].arg[0]);
528 r3 =
reg(
ic[3].arg[0]);
552 uint32_t index0 = addr0 >> 12;
555 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
556 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
557 mips32_loadstore[12](
cpu,
ic);
560 addr0 = (addr0 >> 2) & 0x3ff;
561 addr1 = (addr1 >> 2) & 0x3ff;
562 addr2 = (addr2 >> 2) & 0x3ff;
563 addr3 = (addr3 >> 2) & 0x3ff;
564 addr4 = (addr4 >> 2) & 0x3ff;
565 r0 =
reg(
ic[0].arg[0]);
566 r1 =
reg(
ic[1].arg[0]);
567 r2 =
reg(
ic[2].arg[0]);
568 r3 =
reg(
ic[3].arg[0]);
569 r4 =
reg(
ic[4].arg[0]);
602 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
604 page = (uint32_t *) l3->host_store[x3];
606 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
607 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
611 addr0 = (addr0 >> 2) & 0x3ff;
612 addr1 = (addr1 >> 2) & 0x3ff;
613 addr2 = (addr2 >> 2) & 0x3ff;
614 addr3 = (addr3 >> 2) & 0x3ff;
615 addr4 = (addr4 >> 2) & 0x3ff;
616 r0 =
reg(
ic[0].arg[0]);
617 r1 =
reg(
ic[1].arg[0]);
618 r2 =
reg(
ic[2].arg[0]);
619 r3 =
reg(
ic[3].arg[0]);
620 r4 =
reg(
ic[4].arg[0]);
643 uint32_t index0 = addr0 >> 12;
646 page == NULL || (addr0 & 3) || (addr1 & 3)
647 || ((addr1 ^ addr0) & ~0xfff)) {
648 mips32_loadstore[21](
cpu,
ic);
651 addr0 = (addr0 >> 2) & 0x3ff;
652 addr1 = (addr1 >> 2) & 0x3ff;
678 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
680 page = (uint32_t *) l3->host_load[x3];
682 page == NULL || (addr0 & 3) || (addr1 & 3)
683 || ((addr1 ^ addr0) & ~0xfff)) {
687 addr0 = (addr0 >> 2) & 0x3ff;
688 addr1 = (addr1 >> 2) & 0x3ff;
708 uint32_t index0 = addr0 >> 12;
711 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
712 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
713 mips32_loadstore[21](
cpu,
ic);
716 addr0 = (addr0 >> 2) & 0x3ff;
717 addr1 = (addr1 >> 2) & 0x3ff;
718 addr2 = (addr2 >> 2) & 0x3ff;
748 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
750 page = (uint32_t *) l3->host_load[x3];
752 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
753 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
757 addr0 = (addr0 >> 2) & 0x3ff;
758 addr1 = (addr1 >> 2) & 0x3ff;
759 addr2 = (addr2 >> 2) & 0x3ff;
783 uint32_t index0 = addr0 >> 12;
786 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
787 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
788 mips32_loadstore[21](
cpu,
ic);
791 addr0 = (addr0 >> 2) & 0x3ff;
792 addr1 = (addr1 >> 2) & 0x3ff;
793 addr2 = (addr2 >> 2) & 0x3ff;
794 addr3 = (addr3 >> 2) & 0x3ff;
828 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
830 page = (uint32_t *) l3->host_load[x3];
832 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
833 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
837 addr0 = (addr0 >> 2) & 0x3ff;
838 addr1 = (addr1 >> 2) & 0x3ff;
839 addr2 = (addr2 >> 2) & 0x3ff;
840 addr3 = (addr3 >> 2) & 0x3ff;
868 uint32_t index0 = addr0 >> 12;
871 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
872 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
873 mips32_loadstore[21](
cpu,
ic);
876 addr0 = (addr0 >> 2) & 0x3ff;
877 addr1 = (addr1 >> 2) & 0x3ff;
878 addr2 = (addr2 >> 2) & 0x3ff;
879 addr3 = (addr3 >> 2) & 0x3ff;
880 addr4 = (addr4 >> 2) & 0x3ff;
918 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
920 page = (uint32_t *) l3->host_load[x3];
922 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
923 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
927 addr0 = (addr0 >> 2) & 0x3ff;
928 addr1 = (addr1 >> 2) & 0x3ff;
929 addr2 = (addr2 >> 2) & 0x3ff;
930 addr3 = (addr3 >> 2) & 0x3ff;
931 addr4 = (addr4 >> 2) & 0x3ff;
959 uint32_t index0 = addr0 >> 12;
962 page == NULL || (addr0 & 3) || (addr1 & 3)
963 || ((addr1 ^ addr0) & ~0xfff)) {
964 mips32_loadstore[28](
cpu,
ic);
967 addr0 = (addr0 >> 2) & 0x3ff;
968 addr1 = (addr1 >> 2) & 0x3ff;
969 r0 =
reg(
ic[0].arg[0]);
970 r1 =
reg(
ic[1].arg[0]);
994 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
996 page = (uint32_t *) l3->host_store[x3];
998 page == NULL || (addr0 & 3) || (addr1 & 3)
999 || ((addr1 ^ addr0) & ~0xfff)) {
1003 addr0 = (addr0 >> 2) & 0x3ff;
1004 addr1 = (addr1 >> 2) & 0x3ff;
1005 r0 =
reg(
ic[0].arg[0]);
1006 r1 =
reg(
ic[1].arg[0]);
1024 uint32_t index0 = addr0 >> 12;
1027 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
1028 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
1029 mips32_loadstore[28](
cpu,
ic);
1032 addr0 = (addr0 >> 2) & 0x3ff;
1033 addr1 = (addr1 >> 2) & 0x3ff;
1034 addr2 = (addr2 >> 2) & 0x3ff;
1035 r0 =
reg(
ic[0].arg[0]);
1036 r1 =
reg(
ic[1].arg[0]);
1037 r2 =
reg(
ic[2].arg[0]);
1058 uint32_t x1, x2, x3;
1064 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
1066 page = (uint32_t *) l3->host_store[x3];
1068 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
1069 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff)) {
1073 addr0 = (addr0 >> 2) & 0x3ff;
1074 addr1 = (addr1 >> 2) & 0x3ff;
1075 addr2 = (addr2 >> 2) & 0x3ff;
1076 r0 =
reg(
ic[0].arg[0]);
1077 r1 =
reg(
ic[1].arg[0]);
1078 r2 =
reg(
ic[2].arg[0]);
1099 uint32_t index0 = addr0 >> 12;
1102 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
1103 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
1104 mips32_loadstore[28](
cpu,
ic);
1107 addr0 = (addr0 >> 2) & 0x3ff;
1108 addr1 = (addr1 >> 2) & 0x3ff;
1109 addr2 = (addr2 >> 2) & 0x3ff;
1110 addr3 = (addr3 >> 2) & 0x3ff;
1111 r0 =
reg(
ic[0].arg[0]);
1112 r1 =
reg(
ic[1].arg[0]);
1113 r2 =
reg(
ic[2].arg[0]);
1114 r3 =
reg(
ic[3].arg[0]);
1138 uint32_t x1, x2, x3;
1144 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
1146 page = (uint32_t *) l3->host_store[x3];
1148 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
1149 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff)) {
1153 addr0 = (addr0 >> 2) & 0x3ff;
1154 addr1 = (addr1 >> 2) & 0x3ff;
1155 addr2 = (addr2 >> 2) & 0x3ff;
1156 addr3 = (addr3 >> 2) & 0x3ff;
1157 r0 =
reg(
ic[0].arg[0]);
1158 r1 =
reg(
ic[1].arg[0]);
1159 r2 =
reg(
ic[2].arg[0]);
1160 r3 =
reg(
ic[3].arg[0]);
1184 uint32_t index0 = addr0 >> 12;
1187 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
1188 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
1189 mips32_loadstore[28](
cpu,
ic);
1192 addr0 = (addr0 >> 2) & 0x3ff;
1193 addr1 = (addr1 >> 2) & 0x3ff;
1194 addr2 = (addr2 >> 2) & 0x3ff;
1195 addr3 = (addr3 >> 2) & 0x3ff;
1196 addr4 = (addr4 >> 2) & 0x3ff;
1197 r0 =
reg(
ic[0].arg[0]);
1198 r1 =
reg(
ic[1].arg[0]);
1199 r2 =
reg(
ic[2].arg[0]);
1200 r3 =
reg(
ic[3].arg[0]);
1201 r4 =
reg(
ic[4].arg[0]);
1228 uint32_t x1, x2, x3;
1234 l2 =
cpu->
cd.DYNTRANS_ARCH.l1_64[x1];
1236 page = (uint32_t *) l3->host_store[x3];
1238 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3) || (addr4 & 3)
1239 || ((addr1 ^ addr0) & ~0xfff) || ((addr2 ^ addr0) & ~0xfff) || ((addr3 ^ addr0) & ~0xfff) || ((addr4 ^ addr0) & ~0xfff)) {
1243 addr0 = (addr0 >> 2) & 0x3ff;
1244 addr1 = (addr1 >> 2) & 0x3ff;
1245 addr2 = (addr2 >> 2) & 0x3ff;
1246 addr3 = (addr3 >> 2) & 0x3ff;
1247 addr4 = (addr4 >> 2) & 0x3ff;
1248 r0 =
reg(
ic[0].arg[0]);
1249 r1 =
reg(
ic[1].arg[0]);
1250 r2 =
reg(
ic[2].arg[0]);
1251 r3 =
reg(
ic[3].arg[0]);
1252 r4 =
reg(
ic[4].arg[0]);