alpha_cpu.h Source File
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alpha_cpu.h
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/* GXemul: $Id: alpha_cpu.h,v 1.2 2006-09-01 16:40:57 debug Exp $ */
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/* $NetBSD: alpha_cpu.h,v 1.48 2006/02/16 20:17:13 perry Exp $ */
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#ifndef __ALPHA_ALPHA_CPU_H__
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#define __ALPHA_ALPHA_CPU_H__
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/*
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* Copyright (c) 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
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*
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* Definitions for:
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*
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* Process Control Block
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* Interrupt/Exception/Syscall Stack Frame
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* Processor Status Register
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* Machine Check Error Summary Register
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* Machine Check Logout Area
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* Per CPU state Management of Machine Check Handling
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* Virtual Memory Management
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* Kernel Entry Vectors
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* MMCSR Fault Type Codes
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* Translation Buffer Invalidation
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*
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* and miscellaneous PALcode operations.
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*/
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53
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/*
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* Process Control Block definitions [OSF/1 PALcode Specific]
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*
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* GXemul note: all of these uint64_t were 'unsigned long' in the original
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* NetBSD header file, and the uint32_t were 'unsigned int'.
59
*/
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struct
alpha_pcb
{
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uint64_t
apcb_ksp
;
/* kernel stack ptr */
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uint64_t
apcb_usp
;
/* user stack ptr */
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uint64_t
apcb_ptbr
;
/* page table base reg */
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uint32_t
apcb_cpc
;
/* charged process cycles */
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uint32_t
apcb_asn
;
/* address space number */
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uint64_t
apcb_unique
;
/* process unique value */
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#define apcb_backup_ksp apcb_unique
/* backup kernel stack ptr */
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uint64_t
apcb_flags
;
/* flags; see below */
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uint64_t
apcb_decrsv0
;
/* DEC reserved */
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uint64_t
apcb_decrsv1
;
/* DEC reserved */
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};
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#define ALPHA_PCB_FLAGS_FEN 0x0000000000000001
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#define ALPHA_PCB_FLAGS_PME 0x4000000000000000
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/*
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* Interrupt/Exception/Syscall "Hardware" (really PALcode)
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* Stack Frame definitions
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*
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* These are quadword offsets from the sp on kernel entry, i.e.
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* to get to the value in question you access (sp + (offset * 8)).
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*
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* On syscall entry, A0-A2 aren't written to memory but space
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* _is_ reserved for them.
86
*/
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#define ALPHA_HWFRAME_PS 0
/* processor status register */
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#define ALPHA_HWFRAME_PC 1
/* program counter */
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#define ALPHA_HWFRAME_GP 2
/* global pointer */
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#define ALPHA_HWFRAME_A0 3
/* a0 */
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#define ALPHA_HWFRAME_A1 4
/* a1 */
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#define ALPHA_HWFRAME_A2 5
/* a2 */
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#define ALPHA_HWFRAME_SIZE 6
/* 6 8-byte words */
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/*
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* Processor Status Register [OSF/1 PALcode Specific]
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*
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* Includes user/kernel mode bit, interrupt priority levels, etc.
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*/
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#define ALPHA_PSL_USERMODE 0x0008
/* set -> user mode */
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#define ALPHA_PSL_IPL_MASK 0x0007
/* interrupt level mask */
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#define ALPHA_PSL_IPL_0 0x0000
/* all interrupts enabled */
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#define ALPHA_PSL_IPL_SOFT 0x0001
/* software ints disabled */
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#define ALPHA_PSL_IPL_IO 0x0004
/* I/O dev ints disabled */
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#define ALPHA_PSL_IPL_CLOCK 0x0005
/* clock ints disabled */
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#define ALPHA_PSL_IPL_HIGH 0x0006
/* all but mchecks disabled */
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#define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0
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/* Convenience constants: what must be set/clear in user mode */
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#define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE
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#define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK)
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/*
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* Interrupt Type Code Definitions [OSF/1 PALcode Specific]
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*/
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#define ALPHA_INTR_XPROC 0
/* interprocessor interrupt */
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#define ALPHA_INTR_CLOCK 1
/* clock interrupt */
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#define ALPHA_INTR_ERROR 2
/* correctable error or mcheck */
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#define ALPHA_INTR_DEVICE 3
/* device interrupt */
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#define ALPHA_INTR_PERF 4
/* performance counter */
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#define ALPHA_INTR_PASSIVE 5
/* passive release */
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/*
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* Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
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*
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* The following bits are values as read. On write, _PCE, _SCE, and
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* _MIP are "write 1 to clear."
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*/
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#define ALPHA_MCES_IMP \
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0xffffffff00000000
/* impl. dependent */
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#define ALPHA_MCES_RSVD \
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0x00000000ffffffe0
/* reserved */
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#define ALPHA_MCES_DSC \
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0x0000000000000010
/* disable system correctable error reporting */
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#define ALPHA_MCES_DPC \
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0x0000000000000008
/* disable processor correctable error reporting */
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#define ALPHA_MCES_PCE \
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0x0000000000000004
/* processor correctable error in progress */
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#define ALPHA_MCES_SCE \
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0x0000000000000002
/* system correctable error in progress */
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#define ALPHA_MCES_MIP \
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0x0000000000000001
/* machine check in progress */
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/*
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* Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
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*
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* Note that these are *generic* OSF/1 PALcode specific defines. There are
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* platform variations to these entities.
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*
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* GXemul note: These uint32_t were 'unsigned int' in the original NetBSD
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* header file.
159
*/
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struct
alpha_logout_area
{
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uint32_t
la_frame_size
;
/* frame size */
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uint32_t
la_flags
;
/* flags; see below */
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uint32_t
la_cpu_offset
;
/* offset to cpu area */
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uint32_t
la_system_offset
;
/* offset to system area */
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};
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#define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000
/* OK to continue */
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#define ALPHA_LOGOUT_FLAGS_SE 0x40000000
/* second error */
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#define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff
/* should be zero */
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#define ALPHA_LOGOUT_NOT_BUILT \
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(struct alpha_logout_area *)0xffffffffffffffff)
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#define ALPHA_LOGOUT_PAL_AREA(lap) \
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(unsigned long *)((unsigned char *)(lap) + 16)
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#define ALPHA_LOGOUT_PAL_SIZE(lap) \
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((lap)->la_cpu_offset - 16)
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#define ALPHA_LOGOUT_CPU_AREA(lap) \
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(unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset)
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#define ALPHA_LOGOUT_CPU_SIZE(lap) \
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((lap)->la_system_offset - (lap)->la_cpu_offset)
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#define ALPHA_LOGOUT_SYSTEM_AREA(lap) \
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(unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset)
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#define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \
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((lap)->la_frame_size - (lap)->la_system_offset)
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/* types of machine checks */
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#define ALPHA_SYS_ERROR 0x620
/* System correctable error */
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#define ALPHA_PROC_ERROR 0x630
/* Processor correctable error */
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#define ALPHA_SYS_MCHECK 0x660
/* System machine check */
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#define ALPHA_PROC_MCHECK 0x670
/* Processor machine check */
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/*
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* Virtual Memory Management definitions [OSF/1 PALcode Specific]
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*
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* Includes user and kernel space addresses and information,
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* page table entry definitions, etc.
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*
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* NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS!
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*/
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#define ALPHA_PGSHIFT 13
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#define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT)
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#define ALPHA_USEG_BASE 0
/* virtual */
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#define ALPHA_USEG_END 0x000003ffffffffffULL
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#define ALPHA_K0SEG_BASE 0xfffffc0000000000ULL
/* direct-mapped */
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#define ALPHA_K0SEG_END 0xfffffdffffffffffULL
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#define ALPHA_K1SEG_BASE 0xfffffe0000000000ULL
/* virtual */
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#define ALPHA_K1SEG_END 0xffffffffffffffffULL
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#define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE)
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#define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE)
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#define ALPHA_PTE_VALID 0x0001
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#define ALPHA_PTE_FAULT_ON_READ 0x0002
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#define ALPHA_PTE_FAULT_ON_WRITE 0x0004
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#define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008
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#define ALPHA_PTE_ASM 0x0010
/* addr. space match */
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#define ALPHA_PTE_GRANULARITY 0x0060
/* granularity hint */
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#define ALPHA_PTE_PROT 0xff00
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#define ALPHA_PTE_KR 0x0100
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#define ALPHA_PTE_UR 0x0200
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#define ALPHA_PTE_KW 0x1000
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#define ALPHA_PTE_UW 0x2000
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#define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW)
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#define ALPHA_PTE_SOFTWARE 0x00000000ffff0000
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#define ALPHA_PTE_PALCODE (~ALPHA_PTE_SOFTWARE)
/* shorthand */
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#define ALPHA_PTE_PFN 0xffffffff00000000
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#define ALPHA_PTE_TO_PFN(pte) ((pte) >> 32)
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#define ALPHA_PTE_FROM_PFN(pfn) ((pfn) << 32)
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typedef
unsigned
long
alpha_pt_entry_t
;
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/*
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* Kernel Entry Vectors. [OSF/1 PALcode Specific]
246
*/
247
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#define ALPHA_KENTRY_INT 0
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#define ALPHA_KENTRY_ARITH 1
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#define ALPHA_KENTRY_MM 2
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#define ALPHA_KENTRY_IF 3
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#define ALPHA_KENTRY_UNA 4
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#define ALPHA_KENTRY_SYS 5
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/*
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* MMCSR Fault Type Codes. [OSF/1 PALcode Specific]
257
*/
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#define ALPHA_MMCSR_INVALTRANS 0
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#define ALPHA_MMCSR_ACCESS 1
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#define ALPHA_MMCSR_FOR 2
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#define ALPHA_MMCSR_FOE 3
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#define ALPHA_MMCSR_FOW 4
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/*
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* Instruction Fault Type Codes. [OSF/1 PALcode Specific]
267
*/
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#define ALPHA_IF_CODE_BPT 0
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#define ALPHA_IF_CODE_BUGCHK 1
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#define ALPHA_IF_CODE_GENTRAP 2
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#define ALPHA_IF_CODE_FEN 3
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#define ALPHA_IF_CODE_OPDEC 4
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#ifdef _KERNEL
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/*
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* Translation Buffer Invalidation definitions [OSF/1 PALcode Specific]
279
*/
280
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#define ALPHA_TBIA() alpha_pal_tbi(-2, 0)
/* all TB entries */
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#define ALPHA_TBIAP() alpha_pal_tbi(-1, 0)
/* all per-process */
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#define ALPHA_TBISI(va) alpha_pal_tbi(1, (va))
/* ITB entry for va */
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#define ALPHA_TBISD(va) alpha_pal_tbi(2, (va))
/* DTB entry for va */
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#define ALPHA_TBIS(va) alpha_pal_tbi(3, (va))
/* all for va */
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#endif
/* _KERNEL */
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/*
290
* Bits used in the amask instruction [EV56 and later]
291
*/
292
293
#define ALPHA_AMASK_BWX 0x0001
/* byte/word extension */
294
#define ALPHA_AMASK_FIX 0x0002
/* floating point conv. ext. */
295
#define ALPHA_AMASK_CIX 0x0004
/* count extension */
296
#define ALPHA_AMASK_MVI 0x0100
/* multimedia extension */
297
#define ALPHA_AMASK_PAT 0x0200
/* precise arith. traps */
298
#define ALPHA_AMASK_PMI 0x1000
/* prefetch w/ modify intent */
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300
#define ALPHA_AMASK_ALL (ALPHA_AMASK_BWX|ALPHA_AMASK_FIX| \
301
ALPHA_AMASK_CIX|ALPHA_AMASK_MVI| \
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ALPHA_AMASK_PAT|ALPHA_AMASK_PMI)
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304
#define ALPHA_AMASK_BITS \
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"\20\17PMI\12PAT\11MVI\3CIX\2FIX\1BWX"
306
307
/*
308
* Chip family IDs returned by implver instruction
309
*/
310
311
#define ALPHA_IMPLVER_EV4 0
/* LCA/EV4/EV45 */
312
#define ALPHA_IMPLVER_EV5 1
/* EV5/EV56/PCA56 */
313
#define ALPHA_IMPLVER_EV6 2
/* EV6 */
314
#define ALPHA_IMPLVER_EV7 3
/* EV7/EV79 */
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#ifdef _KERNEL
317
318
/*
319
* Maximum processor ID we allow from `whami', and related constants.
320
*
321
* XXX This is not really processor or PALcode specific, but this is
322
* a convenient place to put these definitions.
323
*
324
* XXX This is clipped at 63 so that we can use `long's for proc bitmasks.
325
*/
326
327
#define ALPHA_WHAMI_MAXID 63
328
#define ALPHA_MAXPROCS (ALPHA_WHAMI_MAXID + 1)
329
330
/*
331
* Misc. support routines.
332
*/
333
const
char
*alpha_dsr_sysname(
void
);
334
335
/*
336
* Stubs for Alpha instructions normally inaccessible from C.
337
*/
338
unsigned
long
alpha_amask(
unsigned
long
);
339
unsigned
long
alpha_implver(
void
);
340
341
#endif
/* _KERNEL */
342
343
#if 0
344
345
/* XXX Expose the insn wrappers to userspace, for now. */
346
347
static
__inline
unsigned
long
348
alpha_rpcc(
void
)
349
{
350
unsigned
long
v0;
351
352
__asm
volatile
(
"rpcc %0"
:
"=r"
(v0));
353
return
(v0);
354
}
355
356
#define alpha_mb() __asm volatile("mb" : : : "memory")
357
#define alpha_wmb() __asm volatile("mb" : : : "memory")
/* XXX */
358
359
#endif
360
361
#if defined(_KERNEL) || defined(_STANDALONE)
362
363
/*
364
* Stubs for OSF/1 PALcode operations.
365
*/
366
#include <machine/pal.h>
367
368
void
alpha_pal_cflush(
unsigned
long
);
369
void
alpha_pal_halt(
void
)
__attribute__
((
__noreturn__
));
370
unsigned
long
_alpha_pal_swpipl(
unsigned
long
);
/* for profiling */
371
void
alpha_pal_wrent(
void
*,
unsigned
long
);
372
void
alpha_pal_wrvptptr(
unsigned
long
);
373
374
#define alpha_pal_draina() __asm volatile("call_pal %0 # PAL_draina" \
375
: : "i" (PAL_draina) : "memory")
376
377
#define alpha_pal_imb() __asm volatile("call_pal %0 # PAL_imb" \
378
: : "i" (PAL_imb) : "memory")
379
380
static
__inline
unsigned
long
381
alpha_pal_rdmces(
void
)
382
{
383
register
unsigned
long
v0 __asm(
"$0"
);
384
385
__asm
volatile
(
"call_pal %1 # PAL_OSF1_rdmces"
386
:
"=r"
(v0)
387
:
"i"
(PAL_OSF1_rdmces)
388
/* clobbers t0, t8..t11 */
389
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
390
391
return
(v0);
392
}
393
394
static
__inline
unsigned
long
395
alpha_pal_rdps(
void
)
396
{
397
register
unsigned
long
v0 __asm(
"$0"
);
398
399
__asm
volatile
(
"call_pal %1 # PAL_OSF1_rdps"
400
:
"=r"
(v0)
401
:
"i"
(PAL_OSF1_rdps)
402
/* clobbers t0, t8..t11 */
403
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
404
405
return
(v0);
406
}
407
408
static
__inline
unsigned
long
409
alpha_pal_rdunique(
void
)
410
{
411
register
unsigned
long
v0 __asm(
"$0"
);
412
413
__asm
volatile
(
"call_pal %1 # PAL_rdunique"
414
:
"=r"
(v0)
415
:
"i"
(PAL_rdunique));
416
417
return
(v0);
418
}
419
420
static
__inline
unsigned
long
421
alpha_pal_rdusp(
void
)
422
{
423
register
unsigned
long
v0 __asm(
"$0"
);
424
425
__asm
volatile
(
"call_pal %1 # PAL_OSF1_rdusp"
426
:
"=r"
(v0)
427
:
"i"
(PAL_OSF1_rdusp)
428
/* clobbers t0, t8..t11 */
429
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
430
431
return
(v0);
432
}
433
434
static
__inline
unsigned
long
435
alpha_pal_rdval(
void
)
436
{
437
register
unsigned
long
v0 __asm(
"$0"
);
438
439
__asm
volatile
(
"call_pal %1 # PAL_OSF1_rdval"
440
:
"=r"
(v0)
441
:
"i"
(PAL_OSF1_rdval)
442
/* clobbers t0, t8..t11 */
443
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
444
445
return
(v0);
446
}
447
448
static
__inline
unsigned
long
449
alpha_pal_swpctx(
unsigned
long
ctx)
450
{
451
register
unsigned
long
a0 __asm(
"$16"
) = ctx;
452
register
unsigned
long
v0 __asm(
"$0"
);
453
454
__asm
volatile
(
"call_pal %2 # PAL_OSF1_swpctx"
455
:
"=r"
(a0),
"=r"
(v0)
456
:
"i"
(PAL_OSF1_swpctx),
"0"
(a0)
457
/* clobbers t0, t8..t11, a0 (above) */
458
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
,
"memory"
);
459
460
return
(v0);
461
}
462
463
static
__inline
unsigned
long
464
alpha_pal_swpipl(
unsigned
long
ipl)
465
{
466
register
unsigned
long
a0 __asm(
"$16"
) = ipl;
467
register
unsigned
long
v0 __asm(
"$0"
);
468
469
__asm
volatile
(
"call_pal %2 # PAL_OSF1_swpipl"
470
:
"=r"
(a0),
"=r"
(v0)
471
:
"i"
(PAL_OSF1_swpipl),
"0"
(a0)
472
/* clobbers t0, t8..t11, a0 (above) */
473
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
,
"memory"
);
474
475
return
(v0);
476
}
477
478
static
__inline
void
479
alpha_pal_tbi(
unsigned
long
op
, vaddr_t va)
480
{
481
register
unsigned
long
a0 __asm(
"$16"
) =
op
;
482
register
unsigned
long
a1 __asm(
"$17"
) = va;
483
484
__asm
volatile
(
"call_pal %2 # PAL_OSF1_tbi"
485
:
"=r"
(a0),
"=r"
(a1)
486
:
"i"
(PAL_OSF1_tbi),
"0"
(a0),
"1"
(a1)
487
/* clobbers t0, t8..t11, a0 (above), a1 (above) */
488
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
489
}
490
491
static
__inline
unsigned
long
492
alpha_pal_whami(
void
)
493
{
494
register
unsigned
long
v0 __asm(
"$0"
);
495
496
__asm
volatile
(
"call_pal %1 # PAL_OSF1_whami"
497
:
"=r"
(v0)
498
:
"i"
(PAL_OSF1_whami)
499
/* clobbers t0, t8..t11 */
500
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
501
502
return
(v0);
503
}
504
505
static
__inline
void
506
alpha_pal_wrfen(
unsigned
long
onoff)
507
{
508
register
unsigned
long
a0 __asm(
"$16"
) = onoff;
509
510
__asm
volatile
(
"call_pal %1 # PAL_OSF1_wrfen"
511
:
"=r"
(a0)
512
:
"i"
(PAL_OSF1_wrfen),
"0"
(a0)
513
/* clobbers t0, t8..t11, a0 (above) */
514
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
515
}
516
517
static
__inline
void
518
alpha_pal_wripir(
unsigned
long
cpu_id)
519
{
520
register
unsigned
long
a0 __asm(
"$16"
) = cpu_id;
521
522
__asm
volatile
(
"call_pal %1 # PAL_ipir"
523
:
"=r"
(a0)
524
:
"i"
(PAL_ipir),
"0"
(a0)
525
/* clobbers t0, t8..t11, a0 (above) */
526
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
527
}
528
529
static
__inline
void
530
alpha_pal_wrunique(
unsigned
long
unique)
531
{
532
register
unsigned
long
a0 __asm(
"$16"
) = unique;
533
534
__asm
volatile
(
"call_pal %1 # PAL_wrunique"
535
:
"=r"
(a0)
536
:
"i"
(PAL_wrunique),
"0"
(a0));
537
}
538
539
static
__inline
void
540
alpha_pal_wrusp(
unsigned
long
usp)
541
{
542
register
unsigned
long
a0 __asm(
"$16"
) = usp;
543
544
__asm
volatile
(
"call_pal %1 # PAL_OSF1_wrusp"
545
:
"=r"
(a0)
546
:
"i"
(PAL_OSF1_wrusp),
"0"
(a0)
547
/* clobbers t0, t8..t11, a0 (above) */
548
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
549
}
550
551
static
__inline
void
552
alpha_pal_wrmces(
unsigned
long
mces)
553
{
554
register
unsigned
long
a0 __asm(
"$16"
) = mces;
555
556
__asm
volatile
(
"call_pal %1 # PAL_OSF1_wrmces"
557
:
"=r"
(a0)
558
:
"i"
(PAL_OSF1_wrmces),
"0"
(a0)
559
/* clobbers t0, t8..t11 */
560
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
561
}
562
563
static
__inline
void
564
alpha_pal_wrval(
unsigned
long
val)
565
{
566
register
unsigned
long
a0 __asm(
"$16"
) = val;
567
568
__asm
volatile
(
"call_pal %1 # PAL_OSF1_wrval"
569
:
"=r"
(a0)
570
:
"i"
(PAL_OSF1_wrval),
"0"
(a0)
571
/* clobbers t0, t8..t11, a0 (above) */
572
:
"$1"
,
"$22"
,
"$23"
,
"$24"
,
"$25"
);
573
}
574
575
#endif
/* _KERNEL */
576
577
#endif
/* __ALPHA_ALPHA_CPU_H__ */
alpha_pcb::apcb_usp
uint64_t apcb_usp
Definition:
alpha_cpu.h:63
alpha_logout_area::la_flags
uint32_t la_flags
Definition:
alpha_cpu.h:163
alpha_logout_area::la_cpu_offset
uint32_t la_cpu_offset
Definition:
alpha_cpu.h:164
alpha_pcb::apcb_ksp
uint64_t apcb_ksp
Definition:
alpha_cpu.h:62
op
char * op[16]
Definition:
generate_arm_dpi.c:34
alpha_pt_entry_t
unsigned long alpha_pt_entry_t
Definition:
alpha_cpu.h:242
alpha_pcb::apcb_asn
uint32_t apcb_asn
Definition:
alpha_cpu.h:66
__attribute__
#define __attribute__(x)
Definition:
dp83932reg.h:15
alpha_pcb::apcb_ptbr
uint64_t apcb_ptbr
Definition:
alpha_cpu.h:64
alpha_pcb::apcb_decrsv0
uint64_t apcb_decrsv0
Definition:
alpha_cpu.h:70
alpha_logout_area
Definition:
alpha_cpu.h:161
alpha_pcb
Definition:
alpha_cpu.h:61
alpha_pcb::apcb_cpc
uint32_t apcb_cpc
Definition:
alpha_cpu.h:65
alpha_pcb::apcb_unique
uint64_t apcb_unique
Definition:
alpha_cpu.h:67
alpha_logout_area::la_frame_size
uint32_t la_frame_size
Definition:
alpha_cpu.h:162
__noreturn__
#define __noreturn__
Definition:
dp83932reg.h:16
alpha_pcb::apcb_decrsv1
uint64_t apcb_decrsv1
Definition:
alpha_cpu.h:71
alpha_logout_area::la_system_offset
uint32_t la_system_offset
Definition:
alpha_cpu.h:165
alpha_pcb::apcb_flags
uint64_t apcb_flags
Definition:
alpha_cpu.h:69
Generated on Tue Aug 25 2020 19:25:06 for GXemul by
1.8.18