dev_sii.cc Source File
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47 #define SII_TICK_SHIFT 14
100 | ((d->
siiregs.dstat + 1) & 0x7);
137 if ((d->
siiregs.slcsr & 7) == 0) {
152 debug(
"[ sii: command INXFER to scsiid=%i ]\n",
155 debug(
"[ sii DMA: TODO ]\n");
157 debug(
"[ sii: transmitting byte 0x%02x using "
158 "PIO mode ]\n", d->
siiregs.data);
178 uint64_t idata = 0, odata = 0;
182 if (relative_addr & 3) {
183 debug(
"[ sii relative_addr = 0x%x !!! ]\n",
184 (
int) relative_addr);
193 regnr = relative_addr / 2;
194 odata = d->
regs[regnr];
196 switch (relative_addr) {
199 debug(
"[ sii: read from SDB (data=0x%04x) ]\n",
202 debug(
"[ sii: write to SDB (data=0x%04x) ]\n",
204 d->
regs[regnr] = idata;
210 debug(
"[ sii: read from CSR (data=0x%04x) ]\n",
213 debug(
"[ sii: write to CSR (data=0x%04x: %s %s "
214 "%s %s %s) ]\n", (
int)idata,
215 idata &
SII_HPM?
"HPM" :
"!hpm",
216 idata &
SII_RSE?
"RSE" :
"!rse",
217 idata &
SII_SLE?
"SLE" :
"!sle",
218 idata &
SII_PCE?
"PCE" :
"!pce",
219 idata &
SII_IE?
"IE" :
"!ie");
220 d->
regs[regnr] = idata;
226 debug(
"[ sii: read from ID (data=0x%04x) ]\n",
229 debug(
"[ sii: write to ID (data=0x%04x: scsi id %i)"
230 " ]\n", (
int)idata, (
int)(idata & 7));
232 debug(
"WARNING: sii ID bit SII_ID_IO not "
235 if ((idata & ~0x7) != 0)
236 debug(
"WARNING: sii ID bits that should "
237 "be zero are not zero!\n");
239 d->
regs[regnr] = idata & 0x7;
245 debug(
"[ sii: read from SLCSR (data=0x%04x: "
246 "scsi_id=%i) ]\n", d->
regs[regnr],
249 debug(
"[ sii: write to SLCSR (data=0x%04x: "
250 "scsi_id=%i) ]\n", (
int)idata, (
int)(idata & 7));
251 if ((idata & ~0x7) != 0)
252 debug(
"WARNING: sii SLCSR bits that should "
253 "be zero are not zero!\n");
255 d->
regs[regnr] = idata & 0x7;
262 debug(
"[ sii: read from DESTAT (data=0x%04x: "
263 "scsi_id=%i) ]\n", d->
regs[regnr],
266 debug(
"[ sii: write to DESTAT (data=0x%04x: "
267 "scsi_id=%i) ]\n", (
int)idata, (
int)(idata & 7));
268 debug(
"WARNING: sii DESTAT is read-only!\n");
275 debug(
"[ sii: read from DATA (data=0x%04x) ]\n",
279 debug(
"[ sii: write to DATA (data=0x%04x) ]\n",
282 d->
regs[regnr] = idata;
288 debug(
"[ sii: read from DMCTRL (data=0x%04x) ]\n",
291 debug(
"[ sii: write to DMCTRL (data=0x%04x: %s) ]\n",
292 (
int)idata, (idata & 3)==0?
"async" :
"sync");
293 if ((idata & ~0x3) != 0)
294 debug(
"WARNING: sii DMCTRL bits that "
295 "should be zero are not zero!\n");
297 d->
regs[regnr] = idata;
303 debug(
"[ sii: read from CSTAT (data=0x%04x) ]\n",
306 debug(
"[ sii: write to CSTAT (data=0x%04x) ]\n",
311 if (idata & (1<<13)) {
312 idata &= ~(1<<13); d->
regs[regnr] &= ~(1<<13);
314 if (idata & (1<<12)) {
315 idata &= ~(1<<12); d->
regs[regnr] &= ~(1<<12);
317 if (idata & (1<<11)) {
319 idata &= ~(1<<11); d->
regs[regnr] &= ~(1<<11);
321 if (idata & (1<<9)) {
323 idata &= ~(1<<9); d->
regs[regnr] &= ~(1<<9);
325 if (idata & (1<<8)) {
327 idata &= ~(1<<8); d->
regs[regnr] &= ~(1<<8);
329 if (idata & (1<<7)) {
330 idata &= ~(1<<7); d->
regs[regnr] &= ~(1<<7);
332 if (idata & (1<<3)) {
333 idata &= ~(1<<3); d->
regs[regnr] &= ~(1<<3);
338 idata |= d->
regs[regnr] & 0x3bf7;
340 d->
regs[regnr] = idata;
346 debug(
"[ sii: read from DSTAT (data=0x%04x) ]\n",
349 debug(
"[ sii: write to DSTAT (data=0x%04x) ]\n",
354 if (idata & (1<<13)) {
355 idata &= ~(1<<13); d->
regs[regnr] &= ~(1<<13);
357 if (idata & (1<<11)) {
359 idata &= ~(1<<11); d->
regs[regnr] &= ~(1<<11);
361 if (idata & (1<<10)) {
363 idata &= ~(1<<10); d->
regs[regnr] &= ~(1<<10);
365 if (idata & (1<<4)) {
367 idata &= ~(1<<4); d->
regs[regnr] &= ~(1<<4);
369 if (idata & (1<<3)) {
370 idata &= ~(1<<3); d->
regs[regnr] &= ~(1<<3);
375 idata |= d->
regs[regnr] & 0x0c17;
377 d->
regs[regnr] = idata;
383 debug(
"[ sii: read from COMM (data=0x%04x) ]\n",
386 debug(
"[ sii: write to COMM (data=0x%04x: %s %s "
387 "%s command=0x%02x rest=0x%02x) ]\n", (
int)idata,
388 idata &
SII_DMA?
"DMA" :
"!dma",
390 idata &
SII_RSL?
"RSL" :
"!rsl",
392 (
int)((idata >> 7) & 0x1f),
394 (
int)(idata & 0x3f));
401 d->
regs[regnr] = idata;
409 debug(
"[ sii: read from DICTRL (data=0x%04x) ]\n",
412 debug(
"[ sii: write to DICTRL (data=0x%04x: "
413 "port=%s) ]\n", (
int)idata,
414 idata &
SII_PRE?
"enabled" :
"disabled");
415 if ((idata & ~0xf) != 0)
416 debug(
"WARNING: sii DICTRL bits that "
417 "should be zero are not zero!\n");
418 d->
regs[regnr] = idata;
424 debug(
"[ sii: read from %08lx (data=0x%04x) ]\n",
425 (
long)relative_addr, d->
regs[regnr]);
427 debug(
"[ sii: write to %08lx (data=0x%04x) ]\n",
428 (
long)relative_addr, (
int)idata);
429 d->
regs[regnr] = idata;
447 memset(d, 0,
sizeof(
struct sii_data));
#define INTERRUPT_CONNECT(name, istruct)
#define INTERRUPT_ASSERT(istruct)
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
void dev_sii_tick(struct cpu *cpu, void *)
int dev_sii_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
#define INTERRUPT_DEASSERT(istruct)
void dev_sii_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, uint64_t buf_start, uint64_t buf_end, char *irq_path)
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
void combine_sii_bits(struct sii_data *d)
#define CHECK_ALLOCATION(ptr)
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