Go to the source code of this file.
◆ CPU_CONSDEV
#define CPU_CONSDEV 1 /* dev_t: console terminal device */ |
◆ CPU_LOADANDRESET
#define CPU_LOADANDRESET 2 /* load kernel image and reset */ |
◆ CPU_MAXID
#define CPU_MAXID 3 /* number of valid machdep ids */ |
◆ CTL_MACHDEP_NAMES
#define CTL_MACHDEP_NAMES |
Value: { \
{ 0, 0 }, \
{ "console_device", CTLTYPE_STRUCT }, \
{ "load_and_reset", CTLTYPE_INT }, \
}
Definition at line 216 of file sh4_cpu.h.
◆ RUN_P1
Value: do { \
void *p; \
__asm volatile("nop;nop;nop;nop;nop;nop;nop;nop"); \
P1: (void)0; \
} while (0)
Definition at line 173 of file sh4_cpu.h.
◆ RUN_P2
Value: do { \
void *p; \
P2: (void)0; \
} while (0)
Definition at line 165 of file sh4_cpu.h.
◆ SH3_P0SEG_BASE
#define SH3_P0SEG_BASE 0x00000000 /* TLB mapped, also U0SEG */ |
◆ SH3_P0SEG_END
#define SH3_P0SEG_END 0x7fffffff |
◆ SH3_P1SEG_BASE
#define SH3_P1SEG_BASE 0x80000000 /* pa == va */ |
◆ SH3_P1SEG_END
#define SH3_P1SEG_END 0x9fffffff |
◆ SH3_P1SEG_TO_P2SEG
#define SH3_P1SEG_TO_P2SEG |
( |
|
x | ) |
((uint32_t)(x) | 0x20000000) |
◆ SH3_P1SEG_TO_PHYS
◆ SH3_P2SEG_BASE
#define SH3_P2SEG_BASE 0xa0000000 /* pa == va, non-cacheable */ |
◆ SH3_P2SEG_END
#define SH3_P2SEG_END 0xbfffffff |
◆ SH3_P2SEG_TO_P1SEG
#define SH3_P2SEG_TO_P1SEG |
( |
|
x | ) |
((uint32_t)(x) & ~0x20000000) |
◆ SH3_P2SEG_TO_PHYS
◆ SH3_P3SEG_BASE
#define SH3_P3SEG_BASE 0xc0000000 /* TLB mapped, kernel mode */ |
◆ SH3_P3SEG_END
#define SH3_P3SEG_END 0xdfffffff |
◆ SH3_P4SEG_BASE
#define SH3_P4SEG_BASE 0xe0000000 /* peripheral space */ |
◆ SH3_P4SEG_END
#define SH3_P4SEG_END 0xffffffff |
◆ SH3_PHYS_MASK
#define SH3_PHYS_MASK 0x1fffffff |
◆ SH3_PHYS_TO_P1SEG
◆ SH3_PHYS_TO_P2SEG
◆ SH4_PRR
◆ SH4_PRR_7750R
#define SH4_PRR_7750R 0x00000100 /* SH7750R */ |
◆ SH4_PRR_7751R
#define SH4_PRR_7751R 0x00000110 /* SH7751R */ |
◆ SH4_PRR_ADDR
#define SH4_PRR_ADDR 0xff000044 /* P4 address */ |
◆ SH4_PRR_MASK
#define SH4_PRR_MASK 0xfffffff0 |
◆ SH4_PVR
◆ SH4_PVR_ADDR
#define SH4_PVR_ADDR 0xff000030 /* P4 address */ |
◆ SH4_PVR_MASK
#define SH4_PVR_MASK 0xffffff00 |
◆ SH4_PVR_SH7750
#define SH4_PVR_SH7750 0x04020500 /* SH7750 */ |
◆ SH4_PVR_SH7750S
#define SH4_PVR_SH7750S 0x04020600 /* SH7750S */ |
◆ SH4_PVR_SH7751
#define SH4_PVR_SH7751 0x04110000 /* SH7751 */ |
◆ SH4_PVR_SH775xR
#define SH4_PVR_SH775xR 0x04050000 /* SH775xR */ |