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Macros | |
#define | SII_SC1_MSK 0x1ff /* All possible signals on the bus */ |
#define | SII_SC1_SEL 0x80 /* SCSI SEL signal active on bus */ |
#define | SII_SC1_ATN 0x08 /* SCSI ATN signal active on bus */ |
#define | SII_SC2_IGS 0x8 /* SCSI drivers for initiator mode */ |
#define | SII_HPM 0x10 /* SII in on an arbitrated SCSI bus */ |
#define | SII_RSE 0x08 /* 1 = respond to reselections */ |
#define | SII_SLE 0x04 /* 1 = respond to selections */ |
#define | SII_PCE 0x02 /* 1 = report parity errors */ |
#define | SII_IE 0x01 /* 1 = enable interrupts */ |
#define | SII_ID_IO 0x8000 /* I/O */ |
#define | SII_IDMSK 0x7 /* ID of target reselected the SII */ |
#define | SII_ASYNC 0x00 /* REQ/ACK Offset for async mode */ |
#define | SII_SYNC 0x03 /* REQ/ACK Offset for sync mode */ |
#define | SII_TCMSK 0x1fff /* transfer count mask */ |
#define | SII_CI 0x8000 /* composite interrupt bit for CSTAT */ |
#define | SII_DI 0x4000 /* composite interrupt bit for DSTAT */ |
#define | SII_RST 0x2000 /* 1 if reset is asserted on SCSI bus */ |
#define | SII_BER 0x1000 /* Bus error */ |
#define | SII_OBC 0x0800 /* Out_en Bit Cleared (DSSI mode) */ |
#define | SII_TZ 0x0400 /* Target pointer Zero (STLP or LTLP is zero) */ |
#define | SII_BUF 0x0200 /* Buffer service - outbound pkt to non-DSSI */ |
#define | SII_LDN 0x0100 /* List element Done */ |
#define | SII_SCH 0x0080 /* State Change */ |
#define | SII_CON 0x0040 /* SII is Connected to another device */ |
#define | SII_DST 0x0020 /* SII was Destination of current transfer */ |
#define | SII_TGT 0x0010 /* SII is operating as a Target */ |
#define | SII_STATE_MSK 0x0070 /* State Mask */ |
#define | SII_SWA 0x0008 /* Selected With Attention */ |
#define | SII_SIP 0x0004 /* Selection In Progress */ |
#define | SII_LST 0x0002 /* Lost arbitration */ |
#define | SII_DNE 0x2000 /* DMA transfer Done */ |
#define | SII_TCZ 0x1000 /* Transfer Count register is Zero */ |
#define | SII_TBE 0x0800 /* Transmit Buffer Empty */ |
#define | SII_IBF 0x0400 /* Input Buffer Full */ |
#define | SII_IPE 0x0200 /* Incoming Parity Error */ |
#define | SII_OBB 0x0100 /* Odd Byte Boundry */ |
#define | SII_MIS 0x0010 /* Phase Mismatch */ |
#define | SII_ATN 0x0008 /* ATN set by initiator if in Target mode */ |
#define | SII_MSG 0x0004 /* current bus state of MSG */ |
#define | SII_CD 0x0002 /* current bus state of C/D */ |
#define | SII_IO 0x0001 /* current bus state of I/O */ |
#define | SII_PHASE_MSK 0x0007 /* Phase Mask */ |
#define | SII_MSG_IN_PHASE 0x7 |
#define | SII_MSG_OUT_PHASE 0x6 |
#define | SII_STATUS_PHASE 0x3 |
#define | SII_CMD_PHASE 0x2 |
#define | SII_DATA_IN_PHASE 0x1 |
#define | SII_DATA_OUT_PHASE 0x0 |
#define | SII_DMA 0x8000 /* DMA mode */ |
#define | SII_DO_RST 0x4000 /* Assert reset on SCSI bus for 25 usecs */ |
#define | SII_RSL 0x1000 /* 0 = select, 1 = reselect desired device */ |
#define | SII_INXFER 0x0800 /* Information Transfer command (I,T) */ |
#define | SII_SELECT 0x0400 /* Select command (D) */ |
#define | SII_REQDATA 0x0200 /* Request Data command (T) */ |
#define | SII_DISCON 0x0100 /* Disconnect command (I,T,D) */ |
#define | SII_CHRESET 0x0080 /* Chip Reset command (I,T,D) */ |
#define | SII_PRE 0x4 /* Enable the SII to drive the SCSI bus */ |
#define | SII_WAIT_COUNT 10000 /* Delay count used for the SII chip */ |
#define | SII_MAX_DMA_XFER_LENGTH 8192 |
Typedefs | |
struct { | |
u_short sdb | |
u_short pad0 | |
u_short sc1 | |
u_short pad1 | |
u_short sc2 | |
u_short pad2 | |
u_short csr | |
u_short pad3 | |
u_short id | |
u_short pad4 | |
u_short slcsr | |
u_short pad5 | |
u_short destat | |
u_short pad6 | |
u_short dstmo | |
u_short pad7 | |
u_short data | |
u_short pad8 | |
u_short dmctrl | |
u_short pad9 | |
u_short dmlotc | |
u_short pad10 | |
u_short dmaddrl | |
u_short pad11 | |
u_short dmaddrh | |
u_short pad12 | |
u_short dmabyte | |
u_short pad13 | |
u_short stlp | |
u_short pad14 | |
u_short ltlp | |
u_short pad15 | |
u_short ilp | |
u_short pad16 | |
u_short dsctrl | |
u_short pad17 | |
u_short cstat | |
u_short pad18 | |
u_short dstat | |
u_short pad19 | |
u_short comm | |
u_short pad20 | |
u_short dictrl | |
u_short pad21 | |
u_short clock | |
u_short pad22 | |
u_short bhdiag | |
u_short pad23 | |
u_short sidiag | |
u_short pad24 | |
u_short dmdiag | |
u_short pad25 | |
u_short mcdiag | |
u_short pad26 | |
} | SIIRegs |
#define SII_ATN 0x0008 /* ATN set by initiator if in Target mode */ |
#define SII_BUF 0x0200 /* Buffer service - outbound pkt to non-DSSI */ |
#define SII_CHRESET 0x0080 /* Chip Reset command (I,T,D) */ |
#define SII_CI 0x8000 /* composite interrupt bit for CSTAT */ |
#define SII_CON 0x0040 /* SII is Connected to another device */ |
#define SII_DI 0x4000 /* composite interrupt bit for DSTAT */ |
#define SII_DO_RST 0x4000 /* Assert reset on SCSI bus for 25 usecs */ |
#define SII_DST 0x0020 /* SII was Destination of current transfer */ |
#define SII_HPM 0x10 /* SII in on an arbitrated SCSI bus */ |
#define SII_IDMSK 0x7 /* ID of target reselected the SII */ |
#define SII_INXFER 0x0800 /* Information Transfer command (I,T) */ |
#define SII_OBC 0x0800 /* Out_en Bit Cleared (DSSI mode) */ |
#define SII_PRE 0x4 /* Enable the SII to drive the SCSI bus */ |
#define SII_RSL 0x1000 /* 0 = select, 1 = reselect desired device */ |
#define SII_RST 0x2000 /* 1 if reset is asserted on SCSI bus */ |
#define SII_SC1_ATN 0x08 /* SCSI ATN signal active on bus */ |
#define SII_SC1_MSK 0x1ff /* All possible signals on the bus */ |
#define SII_SC1_SEL 0x80 /* SCSI SEL signal active on bus */ |
#define SII_SC2_IGS 0x8 /* SCSI drivers for initiator mode */ |
#define SII_TCZ 0x1000 /* Transfer Count register is Zero */ |
#define SII_TZ 0x0400 /* Target pointer Zero (STLP or LTLP is zero) */ |
#define SII_WAIT_COUNT 10000 /* Delay count used for the SII chip */ |
typedef { ... } SIIRegs |
u_short csr |
Definition at line 69 of file siireg.h.
Referenced by DEVICE_ACCESS(), and DEVINIT().
u_short data |
Definition at line 79 of file siireg.h.
Referenced by A__NAME__general(), arm_pop(), arm_push(), bus_pci_data_access(), dev_jazz_dma_controller(), DEVICE_ACCESS(), emul_machine_setup(), CPUComponent::ExecuteMethod(), CacheComponent::ExecuteMethod(), RAMComponent::ExecuteMethod(), load_16bit_word(), load_32bit_word(), load_64bit_word(), FileLoader_raw::LoadIntoComponent(), LS_GENERIC_N(), memory_cache_R3000(), memory_device_update_data(), MEMORY_RW(), memory_warn_about_unimplemented_addr(), memory_writemax64(), net_ip_tcp_connectionreply(), MainbusComponent::ReadData(), CPUComponent::ReadData(), CacheComponent::ReadData(), RAMComponent::ReadData(), store_16bit_word(), store_16bit_word_in_host(), store_32bit_word(), store_32bit_word_in_host(), store_64bit_word(), store_64bit_word_in_host(), store_byte(), store_pointer_and_advance(), MainbusComponent::WriteData(), CPUComponent::WriteData(), CacheComponent::WriteData(), RAMComponent::WriteData(), X(), and Y().
u_short id |
Definition at line 71 of file siireg.h.
Referenced by diskimage_add().