cpu_arm_instr_misc.cc Source File

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cpu_arm_instr_misc.cc
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1 /*
2  * Copyright (C) 2005-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * Misc ARM instructions. Included from cpu_arm_instr.c.
29  */
30 
31 
32 /*
33  * clear_rX: Move #0 into a register. (Optimization hack.)
34  */
35 X(clear_r0) { cpu->cd.arm.r[ 0] = 0; } Y(clear_r0)
36 X(clear_r1) { cpu->cd.arm.r[ 1] = 0; } Y(clear_r1)
37 X(clear_r2) { cpu->cd.arm.r[ 2] = 0; } Y(clear_r2)
38 X(clear_r3) { cpu->cd.arm.r[ 3] = 0; } Y(clear_r3)
39 X(clear_r4) { cpu->cd.arm.r[ 4] = 0; } Y(clear_r4)
40 X(clear_r5) { cpu->cd.arm.r[ 5] = 0; } Y(clear_r5)
41 X(clear_r6) { cpu->cd.arm.r[ 6] = 0; } Y(clear_r6)
42 X(clear_r7) { cpu->cd.arm.r[ 7] = 0; } Y(clear_r7)
43 X(clear_r8) { cpu->cd.arm.r[ 8] = 0; } Y(clear_r8)
44 X(clear_r9) { cpu->cd.arm.r[ 9] = 0; } Y(clear_r9)
45 X(clear_r10) { cpu->cd.arm.r[10] = 0; } Y(clear_r10)
46 X(clear_r11) { cpu->cd.arm.r[11] = 0; } Y(clear_r11)
47 X(clear_r12) { cpu->cd.arm.r[12] = 0; } Y(clear_r12)
48 X(clear_r13) { cpu->cd.arm.r[13] = 0; } Y(clear_r13)
49 X(clear_r14) { cpu->cd.arm.r[14] = 0; } Y(clear_r14)
50 
51 
52 /*
53  * mov1_rX: Move #1 into a register. (Optimization hack.)
54  */
55 X(mov1_r0) { cpu->cd.arm.r[ 0] = 1; } Y(mov1_r0)
56 X(mov1_r1) { cpu->cd.arm.r[ 1] = 1; } Y(mov1_r1)
57 X(mov1_r2) { cpu->cd.arm.r[ 2] = 1; } Y(mov1_r2)
58 X(mov1_r3) { cpu->cd.arm.r[ 3] = 1; } Y(mov1_r3)
59 X(mov1_r4) { cpu->cd.arm.r[ 4] = 1; } Y(mov1_r4)
60 X(mov1_r5) { cpu->cd.arm.r[ 5] = 1; } Y(mov1_r5)
61 X(mov1_r6) { cpu->cd.arm.r[ 6] = 1; } Y(mov1_r6)
62 X(mov1_r7) { cpu->cd.arm.r[ 7] = 1; } Y(mov1_r7)
63 X(mov1_r8) { cpu->cd.arm.r[ 8] = 1; } Y(mov1_r8)
64 X(mov1_r9) { cpu->cd.arm.r[ 9] = 1; } Y(mov1_r9)
65 X(mov1_r10) { cpu->cd.arm.r[10] = 1; } Y(mov1_r10)
66 X(mov1_r11) { cpu->cd.arm.r[11] = 1; } Y(mov1_r11)
67 X(mov1_r12) { cpu->cd.arm.r[12] = 1; } Y(mov1_r12)
68 X(mov1_r13) { cpu->cd.arm.r[13] = 1; } Y(mov1_r13)
69 X(mov1_r14) { cpu->cd.arm.r[14] = 1; } Y(mov1_r14)
70 
71 
72 /*
73  * add1_rX: Add #1 to a register. (Optimization hack.)
74  */
75 X(add1_r0) { cpu->cd.arm.r[ 0] ++; } Y(add1_r0)
76 X(add1_r1) { cpu->cd.arm.r[ 1] ++; } Y(add1_r1)
77 X(add1_r2) { cpu->cd.arm.r[ 2] ++; } Y(add1_r2)
78 X(add1_r3) { cpu->cd.arm.r[ 3] ++; } Y(add1_r3)
79 X(add1_r4) { cpu->cd.arm.r[ 4] ++; } Y(add1_r4)
80 X(add1_r5) { cpu->cd.arm.r[ 5] ++; } Y(add1_r5)
81 X(add1_r6) { cpu->cd.arm.r[ 6] ++; } Y(add1_r6)
82 X(add1_r7) { cpu->cd.arm.r[ 7] ++; } Y(add1_r7)
83 X(add1_r8) { cpu->cd.arm.r[ 8] ++; } Y(add1_r8)
84 X(add1_r9) { cpu->cd.arm.r[ 9] ++; } Y(add1_r9)
85 X(add1_r10) { cpu->cd.arm.r[10] ++; } Y(add1_r10)
86 X(add1_r11) { cpu->cd.arm.r[11] ++; } Y(add1_r11)
87 X(add1_r12) { cpu->cd.arm.r[12] ++; } Y(add1_r12)
88 X(add1_r13) { cpu->cd.arm.r[13] ++; } Y(add1_r13)
89 X(add1_r14) { cpu->cd.arm.r[14] ++; } Y(add1_r14)
90 
91 
Y
Y(clear_r0) X(clear_r1)
Definition: cpu_arm_instr_misc.cc:35
cpu::cd
union cpu::@1 cd
arm_cpu::r
uint32_t r[N_ARM_REGS]
Definition: cpu_arm.h:155
X
X(clear_r0)
Definition: cpu_arm_instr_misc.cc:35
cpu::arm
struct arm_cpu arm
Definition: cpu.h:444
cpu
Definition: cpu.h:326

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