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Macros | |
#define | MALTA_SYSTEMRAM_BASE 0x00000000 /* System RAM: */ |
#define | MALTA_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */ |
#define | MALTA_PCIMEM1_BASE 0x08000000 /* PCI 1 memory: */ |
#define | MALTA_PCIMEM1_SIZE 0x08000000 /* 128 MByte */ |
#define | MALTA_PCIMEM2_BASE 0x10000000 /* PCI 2 memory: */ |
#define | MALTA_PCIMEM2_SIZE 0x08000000 /* 128 MByte */ |
#define | MALTA_PCIMEM3_BASE 0x18000000 /* PCI 3 memory */ |
#define | MALTA_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */ |
#define | MALTA_CORECTRL_BASE 0x1be00000 /* Core control: */ |
#define | MALTA_CORECTRL_SIZE 0x00200000 /* 2 MByte */ |
#define | MALTA_RESERVED_BASE1 0x1c000000 /* Reserved: */ |
#define | MALTA_RESERVED_SIZE1 0x02000000 /* 32 MByte */ |
#define | MALTA_MONITORFLASH_BASE 0x1e000000 /* Monitor Flash: */ |
#define | MALTA_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */ |
#define | MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ |
#define | MALTA_FILEFLASH_BASE 0x1e3e0000 /* File Flash (for monitor): */ |
#define | MALTA_FILEFLASH_SIZE 0x00020000 /* 128 KByte */ |
#define | MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ |
#define | MALTA_RESERVED_BASE2 0x1e400000 /* Reserved: */ |
#define | MALTA_RESERVED_SIZE2 0x00c00000 /* 12 MByte */ |
#define | MALTA_FPGA_BASE 0x1f000000 /* FPGA: */ |
#define | MALTA_FPGA_SIZE 0x00c00000 /* 12 MByte */ |
#define | MALTA_NMISTATUS (MALTA_FPGA_BASE + 0x24) |
#define | MALTA_NMI_SB 0x2 /* Pending NMI from the South Bridge */ |
#define | MALTA_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */ |
#define | MALTA_NMIACK (MALTA_FPGA_BASE + 0x104) |
#define | MALTA_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */ |
#define | MALTA_SWITCH (MALTA_FPGA_BASE + 0x200) |
#define | MALTA_SWITCH_MASK 0xff /* settings of DIP switch S2 */ |
#define | MALTA_STATUS (MALTA_FPGA_BASE + 0x208) |
#define | MALTA_ST_MFWR 0x10 /* Monitor Flash is write protected (JP1) */ |
#define | MALTA_S54 0x08 /* switch S5-4 - set YAMON factory default mode */ |
#define | MALTA_S53 0x04 /* switch S5-3 */ |
#define | MALTA_BIGEND 0x02 /* switch S5-2 - big endian mode */ |
#define | MALTA_JMPRS (MALTA_FPGA_BASE + 0x210) |
#define | MALTA_JMPRS_PCICLK 0x1c /* PCI clock frequency */ |
#define | MALTA_JMPRS_EELOCK 0x02 /* I2C EEPROM is write protected */ |
#define | MALTA_LEDBAR (MALTA_FPGA_BASE + 0x408) |
#define | MALTA_ASCIIWORD (MALTA_FPGA_BASE + 0x410) |
#define | MALTA_ASCII_BASE (MALTA_FPGA_BASE + 0x418) |
#define | MALTA_ASCIIPOS0 0x00 |
#define | MALTA_ASCIIPOS1 0x08 |
#define | MALTA_ASCIIPOS2 0x10 |
#define | MALTA_ASCIIPOS3 0x18 |
#define | MALTA_ASCIIPOS4 0x20 |
#define | MALTA_ASCIIPOS5 0x28 |
#define | MALTA_ASCIIPOS6 0x30 |
#define | MALTA_ASCIIPOS7 0x38 |
#define | MALTA_SOFTRES (MALTA_FPGA_BASE + 0x500) |
#define | MALTA_GORESET 0x42 /* write this to MALTA_SOFTRES for board reset */ |
#define | MALTA_BRKRES (MALTA_FPGA_BASE + 0x508) |
#define | MALTA_BRKRES_MASK 0xff |
#define | MALTA_CBUSUART (MALTA_FPGA_BASE + 0x900) |
#define | MALTA_CBUSUART_INTR 2 |
#define | MALTA_GPIO_BASE (MALTA_FPGA_BASE + 0xa00) |
#define | MALTA_GPOUT 0x0 |
#define | MALTA_GPINP 0x8 |
#define | MALTA_I2C_BASE (MALTA_FPGA_BASE + 0xb00) |
#define | MALTA_I2CINP 0x00 |
#define | MALTA_I2COE 0x08 |
#define | MALTA_I2COUT 0x10 |
#define | MALTA_I2CSEL 0x18 |
#define | MALTA_BOOTROM_BASE 0x1fc00000 /* Boot ROM: */ |
#define | MALTA_BOOTROM_SIZE 0x00400000 /* 4 MByte */ |
#define | MALTA_REVISION 0x1fc00010 |
#define | MALTA_REV_FPGRV 0xff0000 /* CBUS FPGA revision */ |
#define | MALTA_REV_CORID 0x00fc00 /* Core Board ID */ |
#define | MALTA_REV_CORRV 0x000300 /* Core Board Revision */ |
#define | MALTA_REV_PROID 0x0000f0 /* Product ID */ |
#define | MALTA_REV_PRORV 0x00000f /* Product Revision */ |
#define | MALTA_SOUTHBRIDGE_INTR 0 |
#define | MALTA_PCI0_IO_BASE MALTA_PCIMEM3_BASE |
#define | MALTA_PCI0_ADDR(addr) (MALTA_PCI0_IO_BASE + (addr)) |
#define | MALTA_RTCADR 0x70 |
#define | MALTA_RTCDAT 0x71 |
#define | MALTA_SMSC_COM1_ADR 0x3f8 |
#define | MALTA_SMSC_COM2_ADR 0x2f8 |
#define | MALTA_UART0ADR MALTA_SMSC_COM1_ADR |
#define | MALTA_UART1ADR MALTA_SMSC_COM2_ADR |
#define | MALTA_SMSC_1284_ADR 0x378 |
#define | MALTA_1284ADR MALTA_SMSC_1284_ADR |
#define | MALTA_SMSC_FDD_ADR 0x3f0 |
#define | MALTA_FDDADR MALTA_SMSC_FDD_ADR |
#define | MALTA_SMSC_KYBD_ADR 0x60 /* Fixed 0x60, 0x64 */ |
#define | MALTA_KYBDADR MALTA_SMSC_KYBD_ADR |
#define | MALTA_SMSC_MOUSE_ADR MALTA_SMSC_KYBD_ADR |
#define | MALTA_MOUSEADR MALTA_KYBDADR |
#define | MALTA_DMA_PCI_PCIBASE 0x00000000UL |
#define | MALTA_DMA_PCI_PHYSBASE 0x00000000UL |
#define | MALTA_DMA_PCI_SIZE (256 * 1024 * 1024) |
#define | MALTA_DMA_ISA_PCIBASE 0x00800000UL |
#define | MALTA_DMA_ISA_PHYSBASE 0x00000000UL |
#define | MALTA_DMA_ISA_SIZE (8 * 1024 * 1024) |
Functions | |
void | led_bar (uint8_t) |
void | led_display_word (uint32_t) |
void | led_display_str (const char *) |
void | led_display_char (int, uint8_t) |
#define MALTA_1284ADR MALTA_SMSC_1284_ADR |
Definition at line 221 of file maltareg.h.
#define MALTA_ASCII_BASE (MALTA_FPGA_BASE + 0x418) |
Definition at line 154 of file maltareg.h.
#define MALTA_ASCIIPOS0 0x00 |
Definition at line 155 of file maltareg.h.
#define MALTA_ASCIIPOS1 0x08 |
Definition at line 156 of file maltareg.h.
#define MALTA_ASCIIPOS2 0x10 |
Definition at line 157 of file maltareg.h.
#define MALTA_ASCIIPOS3 0x18 |
Definition at line 158 of file maltareg.h.
#define MALTA_ASCIIPOS4 0x20 |
Definition at line 159 of file maltareg.h.
#define MALTA_ASCIIPOS5 0x28 |
Definition at line 160 of file maltareg.h.
#define MALTA_ASCIIPOS6 0x30 |
Definition at line 161 of file maltareg.h.
#define MALTA_ASCIIPOS7 0x38 |
Definition at line 162 of file maltareg.h.
#define MALTA_ASCIIWORD (MALTA_FPGA_BASE + 0x410) |
Definition at line 153 of file maltareg.h.
#define MALTA_BIGEND 0x02 /* switch S5-2 - big endian mode */ |
Definition at line 146 of file maltareg.h.
#define MALTA_BOOTROM_BASE 0x1fc00000 /* Boot ROM: */ |
Definition at line 196 of file maltareg.h.
#define MALTA_BOOTROM_SIZE 0x00400000 /* 4 MByte */ |
Definition at line 197 of file maltareg.h.
#define MALTA_BRKRES (MALTA_FPGA_BASE + 0x508) |
Definition at line 171 of file maltareg.h.
#define MALTA_BRKRES_MASK 0xff |
Definition at line 172 of file maltareg.h.
#define MALTA_CBUSUART (MALTA_FPGA_BASE + 0x900) |
Definition at line 174 of file maltareg.h.
#define MALTA_CBUSUART_INTR 2 |
Definition at line 184 of file maltareg.h.
#define MALTA_CORECTRL_BASE 0x1be00000 /* Core control: */ |
Definition at line 111 of file maltareg.h.
#define MALTA_CORECTRL_SIZE 0x00200000 /* 2 MByte */ |
Definition at line 112 of file maltareg.h.
#define MALTA_DMA_ISA_PCIBASE 0x00800000UL |
Definition at line 236 of file maltareg.h.
#define MALTA_DMA_ISA_PHYSBASE 0x00000000UL |
Definition at line 237 of file maltareg.h.
#define MALTA_DMA_ISA_SIZE (8 * 1024 * 1024) |
Definition at line 238 of file maltareg.h.
#define MALTA_DMA_PCI_PCIBASE 0x00000000UL |
Definition at line 232 of file maltareg.h.
#define MALTA_DMA_PCI_PHYSBASE 0x00000000UL |
Definition at line 233 of file maltareg.h.
#define MALTA_DMA_PCI_SIZE (256 * 1024 * 1024) |
Definition at line 234 of file maltareg.h.
#define MALTA_FDDADR MALTA_SMSC_FDD_ADR |
Definition at line 224 of file maltareg.h.
#define MALTA_FILEFLASH_BASE 0x1e3e0000 /* File Flash (for monitor): */ |
Definition at line 121 of file maltareg.h.
#define MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ |
Definition at line 124 of file maltareg.h.
#define MALTA_FILEFLASH_SIZE 0x00020000 /* 128 KByte */ |
Definition at line 122 of file maltareg.h.
#define MALTA_FPGA_BASE 0x1f000000 /* FPGA: */ |
Definition at line 129 of file maltareg.h.
#define MALTA_FPGA_SIZE 0x00c00000 /* 12 MByte */ |
Definition at line 130 of file maltareg.h.
#define MALTA_GORESET 0x42 /* write this to MALTA_SOFTRES for board reset */ |
Definition at line 165 of file maltareg.h.
#define MALTA_GPINP 0x8 |
Definition at line 188 of file maltareg.h.
#define MALTA_GPIO_BASE (MALTA_FPGA_BASE + 0xa00) |
Definition at line 186 of file maltareg.h.
#define MALTA_GPOUT 0x0 |
Definition at line 187 of file maltareg.h.
#define MALTA_I2C_BASE (MALTA_FPGA_BASE + 0xb00) |
Definition at line 190 of file maltareg.h.
#define MALTA_I2CINP 0x00 |
Definition at line 191 of file maltareg.h.
#define MALTA_I2COE 0x08 |
Definition at line 192 of file maltareg.h.
#define MALTA_I2COUT 0x10 |
Definition at line 193 of file maltareg.h.
#define MALTA_I2CSEL 0x18 |
Definition at line 194 of file maltareg.h.
#define MALTA_JMPRS (MALTA_FPGA_BASE + 0x210) |
Definition at line 148 of file maltareg.h.
#define MALTA_JMPRS_EELOCK 0x02 /* I2C EEPROM is write protected */ |
Definition at line 150 of file maltareg.h.
#define MALTA_JMPRS_PCICLK 0x1c /* PCI clock frequency */ |
Definition at line 149 of file maltareg.h.
#define MALTA_KYBDADR MALTA_SMSC_KYBD_ADR |
Definition at line 227 of file maltareg.h.
#define MALTA_LEDBAR (MALTA_FPGA_BASE + 0x408) |
Definition at line 152 of file maltareg.h.
#define MALTA_MONITORFLASH_BASE 0x1e000000 /* Monitor Flash: */ |
Definition at line 117 of file maltareg.h.
#define MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ |
Definition at line 119 of file maltareg.h.
#define MALTA_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */ |
Definition at line 118 of file maltareg.h.
#define MALTA_MOUSEADR MALTA_KYBDADR |
Definition at line 229 of file maltareg.h.
#define MALTA_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */ |
Definition at line 134 of file maltareg.h.
#define MALTA_NMI_SB 0x2 /* Pending NMI from the South Bridge */ |
Definition at line 133 of file maltareg.h.
#define MALTA_NMIACK (MALTA_FPGA_BASE + 0x104) |
Definition at line 136 of file maltareg.h.
#define MALTA_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */ |
Definition at line 137 of file maltareg.h.
#define MALTA_NMISTATUS (MALTA_FPGA_BASE + 0x24) |
Definition at line 132 of file maltareg.h.
#define MALTA_PCI0_ADDR | ( | addr | ) | (MALTA_PCI0_IO_BASE + (addr)) |
Definition at line 210 of file maltareg.h.
#define MALTA_PCI0_IO_BASE MALTA_PCIMEM3_BASE |
Definition at line 209 of file maltareg.h.
#define MALTA_PCIMEM1_BASE 0x08000000 /* PCI 1 memory: */ |
Definition at line 102 of file maltareg.h.
#define MALTA_PCIMEM1_SIZE 0x08000000 /* 128 MByte */ |
Definition at line 103 of file maltareg.h.
#define MALTA_PCIMEM2_BASE 0x10000000 /* PCI 2 memory: */ |
Definition at line 105 of file maltareg.h.
#define MALTA_PCIMEM2_SIZE 0x08000000 /* 128 MByte */ |
Definition at line 106 of file maltareg.h.
#define MALTA_PCIMEM3_BASE 0x18000000 /* PCI 3 memory */ |
Definition at line 108 of file maltareg.h.
#define MALTA_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */ |
Definition at line 109 of file maltareg.h.
#define MALTA_RESERVED_BASE1 0x1c000000 /* Reserved: */ |
Definition at line 114 of file maltareg.h.
#define MALTA_RESERVED_BASE2 0x1e400000 /* Reserved: */ |
Definition at line 126 of file maltareg.h.
#define MALTA_RESERVED_SIZE1 0x02000000 /* 32 MByte */ |
Definition at line 115 of file maltareg.h.
#define MALTA_RESERVED_SIZE2 0x00c00000 /* 12 MByte */ |
Definition at line 127 of file maltareg.h.
#define MALTA_REV_CORID 0x00fc00 /* Core Board ID */ |
Definition at line 201 of file maltareg.h.
#define MALTA_REV_CORRV 0x000300 /* Core Board Revision */ |
Definition at line 202 of file maltareg.h.
#define MALTA_REV_FPGRV 0xff0000 /* CBUS FPGA revision */ |
Definition at line 200 of file maltareg.h.
#define MALTA_REV_PROID 0x0000f0 /* Product ID */ |
Definition at line 203 of file maltareg.h.
#define MALTA_REV_PRORV 0x00000f /* Product Revision */ |
Definition at line 204 of file maltareg.h.
#define MALTA_REVISION 0x1fc00010 |
Definition at line 199 of file maltareg.h.
#define MALTA_RTCADR 0x70 |
Definition at line 212 of file maltareg.h.
#define MALTA_RTCDAT 0x71 |
Definition at line 213 of file maltareg.h.
#define MALTA_S53 0x04 /* switch S5-3 */ |
Definition at line 145 of file maltareg.h.
#define MALTA_S54 0x08 /* switch S5-4 - set YAMON factory default mode */ |
Definition at line 144 of file maltareg.h.
#define MALTA_SMSC_1284_ADR 0x378 |
Definition at line 220 of file maltareg.h.
#define MALTA_SMSC_COM1_ADR 0x3f8 |
Definition at line 215 of file maltareg.h.
#define MALTA_SMSC_COM2_ADR 0x2f8 |
Definition at line 216 of file maltareg.h.
#define MALTA_SMSC_FDD_ADR 0x3f0 |
Definition at line 223 of file maltareg.h.
#define MALTA_SMSC_KYBD_ADR 0x60 /* Fixed 0x60, 0x64 */ |
Definition at line 226 of file maltareg.h.
#define MALTA_SMSC_MOUSE_ADR MALTA_SMSC_KYBD_ADR |
Definition at line 228 of file maltareg.h.
#define MALTA_SOFTRES (MALTA_FPGA_BASE + 0x500) |
Definition at line 164 of file maltareg.h.
#define MALTA_SOUTHBRIDGE_INTR 0 |
Definition at line 207 of file maltareg.h.
#define MALTA_ST_MFWR 0x10 /* Monitor Flash is write protected (JP1) */ |
Definition at line 143 of file maltareg.h.
#define MALTA_STATUS (MALTA_FPGA_BASE + 0x208) |
Definition at line 142 of file maltareg.h.
#define MALTA_SWITCH (MALTA_FPGA_BASE + 0x200) |
Definition at line 139 of file maltareg.h.
#define MALTA_SWITCH_MASK 0xff /* settings of DIP switch S2 */ |
Definition at line 140 of file maltareg.h.
#define MALTA_SYSTEMRAM_BASE 0x00000000 /* System RAM: */ |
Definition at line 99 of file maltareg.h.
#define MALTA_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */ |
Definition at line 100 of file maltareg.h.
#define MALTA_UART0ADR MALTA_SMSC_COM1_ADR |
Definition at line 217 of file maltareg.h.
#define MALTA_UART1ADR MALTA_SMSC_COM2_ADR |
Definition at line 218 of file maltareg.h.
void led_bar | ( | uint8_t | ) |
void led_display_char | ( | int | , |
uint8_t | |||
) |
void led_display_str | ( | const char * | ) |
void led_display_word | ( | uint32_t | ) |