17 #include <rte_compat.h>
46 RTE_PMD_I40E_PKG_OP_UNDEFINED = 0,
50 RTE_PMD_I40E_PKG_OP_MAX = 32
57 RTE_PMD_I40E_PKG_INFO_UNDEFINED = 0,
58 RTE_PMD_I40E_PKG_INFO_GLOBAL_HEADER,
59 RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES_SIZE,
60 RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES,
61 RTE_PMD_I40E_PKG_INFO_GLOBAL_MAX = 1024,
62 RTE_PMD_I40E_PKG_INFO_HEADER,
63 RTE_PMD_I40E_PKG_INFO_DEVID_NUM,
64 RTE_PMD_I40E_PKG_INFO_DEVID_LIST,
65 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM,
66 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST,
67 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM,
68 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST,
69 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM,
70 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST,
71 RTE_PMD_I40E_PKG_INFO_MAX = (int)0xFFFFFFFF
78 RTE_PMD_I40E_RSS_QUEUE_REGION_UNDEFINED,
99 RTE_PMD_I40E_RSS_QUEUE_REGION_INFO_GET,
100 RTE_PMD_I40E_RSS_QUEUE_REGION_OP_MAX
103 #define RTE_PMD_I40E_DDP_NAME_SIZE 32
104 #define RTE_PMD_I40E_PCTYPE_MAX 64
105 #define RTE_PMD_I40E_REGION_MAX_NUM 8
106 #define RTE_PMD_I40E_MAX_USER_PRIORITY 8
123 uint32_t vendor_dev_id;
124 uint32_t sub_vendor_dev_id;
135 uint8_t name[RTE_PMD_I40E_DDP_NAME_SIZE];
138 #define RTE_PMD_I40E_DDP_OWNER_UNKNOWN 0xFF
148 #define RTE_PMD_I40E_PROTO_NUM 6
149 #define RTE_PMD_I40E_PROTO_UNUSED 0xFF
156 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
164 uint8_t protocols[RTE_PMD_I40E_PROTO_NUM];
172 #define RTE_PMD_I40E_PTYPE_USER_DEFINE_MASK 0x80000000
174 struct rte_pmd_i40e_ptype_mapping {
199 struct rte_pmd_i40e_queue_region_info {
203 uint8_t queue_start_index;
207 uint8_t user_priority_num;
209 uint8_t user_priority[RTE_PMD_I40E_MAX_USER_PRIORITY];
211 uint8_t flowtype_num;
217 uint8_t hw_flowtype[RTE_PMD_I40E_PCTYPE_MAX];
220 struct rte_pmd_i40e_queue_regions {
222 uint16_t queue_region_number;
223 struct rte_pmd_i40e_queue_region_info
224 region[RTE_PMD_I40E_REGION_MAX_NUM];
231 RTE_PMD_I40E_PKT_TEMPLATE_ACCEPT,
232 RTE_PMD_I40E_PKT_TEMPLATE_REJECT,
233 RTE_PMD_I40E_PKT_TEMPLATE_PASSTHRU,
294 enum rte_pmd_i40e_inset_type {
301 struct rte_pmd_i40e_inset_mask {
306 struct rte_pmd_i40e_inset {
308 struct rte_pmd_i40e_inset_mask mask[2];
573 uint64_t vf_mask, uint8_t on);
749 uint8_t *info, uint32_t size,
786 struct rte_pmd_i40e_ptype_mapping *mapping_items,
817 struct rte_pmd_i40e_ptype_mapping *mapping_items,
861 #define RTE_PMD_I40E_PCTYPE_MAX 64
862 #define RTE_PMD_I40E_FLOW_TYPE_MAX 64
864 struct rte_pmd_i40e_flow_type_mapping {
888 struct rte_pmd_i40e_flow_type_mapping *mapping_items,
905 struct rte_pmd_i40e_flow_type_mapping *mapping_items);
945 int rte_pmd_i40e_cfg_hash_inset(uint16_t port,
946 uint64_t pctype, uint64_t inset);
966 struct rte_pmd_i40e_inset *inset,
967 enum rte_pmd_i40e_inset_type inset_type);
987 struct rte_pmd_i40e_inset *inset,
988 enum rte_pmd_i40e_inset_type inset_type);
1009 bit_idx = 63 - field_idx;
1010 if (inset & (1ULL << bit_idx))
1035 bit_idx = 63 - field_idx;
1036 *inset = *inset | (1ULL << bit_idx);
1060 bit_idx = 63 - field_idx;
1061 *inset = *inset & ~(1ULL << bit_idx);