[−][src]Module core::arch::arm
Platform-specific intrinsics for the arm
platform.
See the module documentation for more details.
Structs
APSR | ExperimentalARM Application Program Status Register |
SY | ExperimentalARM Full system is the required shareability domain, reads and writes are the required access types |
float32x2_t | ExperimentalARM ARM-specific 64-bit wide vector of two packed |
float32x4_t | ExperimentalARM ARM-specific 128-bit wide vector of four packed |
int16x2_t | ExperimentalARM ARM-specific 32-bit wide vector of two packed |
int16x4_t | ExperimentalARM ARM-specific 64-bit wide vector of four packed |
int16x8_t | ExperimentalARM ARM-specific 128-bit wide vector of eight packed |
int32x2_t | ExperimentalARM ARM-specific 64-bit wide vector of two packed |
int32x4_t | ExperimentalARM ARM-specific 128-bit wide vector of four packed |
int64x1_t | ExperimentalARM ARM-specific 64-bit wide vector of one packed |
int64x2_t | ExperimentalARM ARM-specific 128-bit wide vector of two packed |
int8x4_t | ExperimentalARM ARM-specific 32-bit wide vector of four packed |
int8x8_t | ExperimentalARM ARM-specific 64-bit wide vector of eight packed |
int8x16_t | ExperimentalARM ARM-specific 128-bit wide vector of sixteen packed |
int8x8x2_t | ExperimentalARM ARM-specific type containing two |
int8x8x3_t | ExperimentalARM ARM-specific type containing three |
int8x8x4_t | ExperimentalARM ARM-specific type containing four |
poly16x4_t | ExperimentalARM ARM-specific 64-bit wide vector of four packed |
poly16x8_t | ExperimentalARM ARM-specific 128-bit wide vector of eight packed |
poly8x8_t | ExperimentalARM ARM-specific 64-bit wide polynomial vector of eight packed |
poly8x16_t | ExperimentalARM ARM-specific 128-bit wide vector of sixteen packed |
poly8x8x2_t | ExperimentalARM ARM-specific type containing two |
poly8x8x3_t | ExperimentalARM ARM-specific type containing three |
poly8x8x4_t | ExperimentalARM ARM-specific type containing four |
uint16x2_t | ExperimentalARM ARM-specific 32-bit wide vector of two packed |
uint16x4_t | ExperimentalARM ARM-specific 64-bit wide vector of four packed |
uint16x8_t | ExperimentalARM ARM-specific 128-bit wide vector of eight packed |
uint32x2_t | ExperimentalARM ARM-specific 64-bit wide vector of two packed |
uint32x4_t | ExperimentalARM ARM-specific 128-bit wide vector of four packed |
uint64x1_t | ExperimentalARM ARM-specific 64-bit wide vector of one packed |
uint64x2_t | ExperimentalARM ARM-specific 128-bit wide vector of two packed |
uint8x4_t | ExperimentalARM ARM-specific 32-bit wide vector of four packed |
uint8x8_t | ExperimentalARM ARM-specific 64-bit wide vector of eight packed |
uint8x16_t | ExperimentalARM ARM-specific 128-bit wide vector of sixteen packed |
uint8x8x2_t | ExperimentalARM ARM-specific type containing two |
uint8x8x3_t | ExperimentalARM ARM-specific type containing three |
uint8x8x4_t | ExperimentalARM ARM-specific type containing four |
Functions
__breakpoint⚠ | ExperimentalARM Inserts a breakpoint instruction. |
__dmb⚠ | ExperimentalARM Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction. |
__dsb⚠ | ExperimentalARM Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction. |
__isb⚠ | ExperimentalARM Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction. |
__ldrex⚠ | ExperimentalARM Executes a exclusive LDR instruction for 32 bit value. |
__nop⚠ | ExperimentalARM Generates an unspecified no-op instruction. |
__qadd⚠ | ExperimentalARM Signed saturating addition |
__qadd8⚠ | ExperimentalARM Saturating four 8-bit integer additions |
__qadd16⚠ | ExperimentalARM Saturating two 16-bit integer additions |
__qasx⚠ | ExperimentalARM Returns the 16-bit signed saturated equivalent of |
__qdbl⚠ | ExperimentalARM Insert a QADD instruction |
__qsax⚠ | ExperimentalARM Returns the 16-bit signed saturated equivalent of |
__qsub⚠ | ExperimentalARM Signed saturating subtraction |
__qsub8⚠ | ExperimentalARM Saturating two 8-bit integer subtraction |
__qsub16⚠ | ExperimentalARM Saturating two 16-bit integer subtraction |
__rsr⚠ | ExperimentalARM Reads a 32-bit system register |
__rsrp⚠ | ExperimentalARM Reads a system register containing an address |
__sadd8⚠ | ExperimentalARM Returns the 8-bit signed saturated equivalent of |
__sadd16⚠ | ExperimentalARM Returns the 16-bit signed saturated equivalent of |
__sasx⚠ | ExperimentalARM Returns the 16-bit signed equivalent of |
__sel⚠ | ExperimentalARM Select bytes from each operand according to APSR GE flags |
__sev⚠ | ExperimentalARM Generates a SEV (send a global event) hint instruction. |
__shadd8⚠ | ExperimentalARM Signed halving parallel byte-wise addition. |
__shadd16⚠ | ExperimentalARM Signed halving parallel halfword-wise addition. |
__shsub8⚠ | ExperimentalARM Signed halving parallel byte-wise subtraction. |
__shsub16⚠ | ExperimentalARM Signed halving parallel halfword-wise subtraction. |
__smlabb⚠ | ExperimentalARM Insert a SMLABB instruction |
__smlabt⚠ | ExperimentalARM Insert a SMLABT instruction |
__smlad⚠ | ExperimentalARM Dual 16-bit Signed Multiply with Addition of products and 32-bit accumulation. |
__smlatb⚠ | ExperimentalARM Insert a SMLATB instruction |
__smlatt⚠ | ExperimentalARM Insert a SMLATT instruction |
__smlawb⚠ | ExperimentalARM Insert a SMLAWB instruction |
__smlawt⚠ | ExperimentalARM Insert a SMLAWT instruction |
__smlsd⚠ | ExperimentalARM Dual 16-bit Signed Multiply with Subtraction of products and 32-bit accumulation and overflow detection. |
__smuad⚠ | ExperimentalARM Signed Dual Multiply Add. |
__smuadx⚠ | ExperimentalARM Signed Dual Multiply Add Reversed. |
__smulbb⚠ | ExperimentalARM Insert a SMULBB instruction |
__smulbt⚠ | ExperimentalARM Insert a SMULTB instruction |
__smultb⚠ | ExperimentalARM Insert a SMULTB instruction |
__smultt⚠ | ExperimentalARM Insert a SMULTT instruction |
__smulwb⚠ | ExperimentalARM Insert a SMULWB instruction |
__smulwt⚠ | ExperimentalARM Insert a SMULWT instruction |
__smusd⚠ | ExperimentalARM Signed Dual Multiply Subtract. |
__smusdx⚠ | ExperimentalARM Signed Dual Multiply Subtract Reversed. |
__ssub8⚠ | ExperimentalARM Inserts a |
__strex⚠ | ExperimentalARM Executes a exclusive STR instruction for 32 bit values |
__usad8⚠ | ExperimentalARM Sum of 8-bit absolute differences. |
__usada8⚠ | ExperimentalARM Sum of 8-bit absolute differences and constant. |
__usub8⚠ | ExperimentalARM Inserts a |
__wfe⚠ | ExperimentalARM Generates a WFE (wait for event) hint instruction, or nothing. |
__wfi⚠ | ExperimentalARM Generates a WFI (wait for interrupt) hint instruction, or nothing. |
__wsr⚠ | ExperimentalARM Writes a 32-bit system register |
__wsrp⚠ | ExperimentalARM Writes a system register containing an address |
__yield⚠ | ExperimentalARM Generates a YIELD hint instruction. |
_rev_u16⚠ | ExperimentalARM Reverse the order of the bytes. |
_rev_u32⚠ | ExperimentalARM Reverse the order of the bytes. |
udf⚠ | ExperimentalARM Generates the trap instruction |
vadd_f32⚠ | Experimentalneon and v7 and ARMVector add. |
vadd_s8⚠ | Experimentalneon and v7 and ARMVector add. |
vadd_s16⚠ | Experimentalneon and v7 and ARMVector add. |
vadd_s32⚠ | Experimentalneon and v7 and ARMVector add. |
vadd_u8⚠ | Experimentalneon and v7 and ARMVector add. |
vadd_u16⚠ | Experimentalneon and v7 and ARMVector add. |
vadd_u32⚠ | Experimentalneon and v7 and ARMVector add. |
vaddl_s8⚠ | Experimentalneon and v7 and ARMVector long add. |
vaddl_s16⚠ | Experimentalneon and v7 and ARMVector long add. |
vaddl_s32⚠ | Experimentalneon and v7 and ARMVector long add. |
vaddl_u8⚠ | Experimentalneon and v7 and ARMVector long add. |
vaddl_u16⚠ | Experimentalneon and v7 and ARMVector long add. |
vaddl_u32⚠ | Experimentalneon and v7 and ARMVector long add. |
vaddq_f32⚠ | Experimentalneon and v7 and ARMVector add. |
vaddq_s8⚠ | Experimentalneon and v7 and ARMVector add. |
vaddq_s16⚠ | Experimentalneon and v7 and ARMVector add. |
vaddq_s32⚠ | Experimentalneon and v7 and ARMVector add. |
vaddq_s64⚠ | Experimentalneon and v7 and ARMVector add. |
vaddq_u8⚠ | Experimentalneon and v7 and ARMVector add. |
vaddq_u16⚠ | Experimentalneon and v7 and ARMVector add. |
vaddq_u32⚠ | Experimentalneon and v7 and ARMVector add. |
vaddq_u64⚠ | Experimentalneon and v7 and ARMVector add. |
vand_s8⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vand_s16⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vand_s32⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vand_s64⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vand_u8⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vand_u16⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vand_u32⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vand_u64⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vandq_s8⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vandq_s16⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vandq_s32⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vandq_s64⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vandq_u8⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vandq_u16⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vandq_u32⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vandq_u64⚠ | Experimentalneon and v7 and ARMVector bitwise and |
vceq_f32⚠ | Experimentalneon and v7 and ARMFloating-point compare equal |
vceq_s8⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceq_s16⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceq_s32⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceq_u8⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceq_u16⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceq_u32⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceqq_f32⚠ | Experimentalneon and v7 and ARMFloating-point compare equal |
vceqq_s8⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceqq_s16⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceqq_s32⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceqq_u8⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceqq_u16⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vceqq_u32⚠ | Experimentalneon and v7 and ARMCompare bitwise Equal (vector) |
vcge_f32⚠ | Experimentalneon and v7 and ARMFloating-point compare greater than or equal |
vcge_s8⚠ | Experimentalneon and v7 and ARMCompare signed greater than or equal |
vcge_s16⚠ | Experimentalneon and v7 and ARMCompare signed greater than or equal |
vcge_s32⚠ | Experimentalneon and v7 and ARMCompare signed greater than or equal |
vcge_u8⚠ | Experimentalneon and v7 and ARMCompare unsigned greater than or equal |
vcge_u16⚠ | Experimentalneon and v7 and ARMCompare unsigned greater than or equal |
vcge_u32⚠ | Experimentalneon and v7 and ARMCompare unsigned greater than or equal |
vcgeq_f32⚠ | Experimentalneon and v7 and ARMFloating-point compare greater than or equal |
vcgeq_s8⚠ | Experimentalneon and v7 and ARMCompare signed greater than or equal |
vcgeq_s16⚠ | Experimentalneon and v7 and ARMCompare signed greater than or equal |
vcgeq_s32⚠ | Experimentalneon and v7 and ARMCompare signed greater than or equal |
vcgeq_u8⚠ | Experimentalneon and v7 and ARMCompare unsigned greater than or equal |
vcgeq_u16⚠ | Experimentalneon and v7 and ARMCompare unsigned greater than or equal |
vcgeq_u32⚠ | Experimentalneon and v7 and ARMCompare unsigned greater than or equal |
vcgt_f32⚠ | Experimentalneon and v7 and ARMFloating-point compare greater than |
vcgt_s8⚠ | Experimentalneon and v7 and ARMCompare signed greater than |
vcgt_s16⚠ | Experimentalneon and v7 and ARMCompare signed greater than |
vcgt_s32⚠ | Experimentalneon and v7 and ARMCompare signed greater than |
vcgt_u8⚠ | Experimentalneon and v7 and ARMCompare unsigned highe |
vcgt_u16⚠ | Experimentalneon and v7 and ARMCompare unsigned highe |
vcgt_u32⚠ | Experimentalneon and v7 and ARMCompare unsigned highe |
vcgtq_f32⚠ | Experimentalneon and v7 and ARMFloating-point compare greater than |
vcgtq_s8⚠ | Experimentalneon and v7 and ARMCompare signed greater than |
vcgtq_s16⚠ | Experimentalneon and v7 and ARMCompare signed greater than |
vcgtq_s32⚠ | Experimentalneon and v7 and ARMCompare signed greater than |
vcgtq_u8⚠ | Experimentalneon and v7 and ARMCompare unsigned highe |
vcgtq_u16⚠ | Experimentalneon and v7 and ARMCompare unsigned highe |
vcgtq_u32⚠ | Experimentalneon and v7 and ARMCompare unsigned highe |
vcle_f32⚠ | Experimentalneon and v7 and ARMFloating-point compare less than or equal |
vcle_s8⚠ | Experimentalneon and v7 and ARMCompare signed less than or equal |
vcle_s16⚠ | Experimentalneon and v7 and ARMCompare signed less than or equal |
vcle_s32⚠ | Experimentalneon and v7 and ARMCompare signed less than or equal |
vcle_u8⚠ | Experimentalneon and v7 and ARMCompare unsigned less than or equal |
vcle_u16⚠ | Experimentalneon and v7 and ARMCompare unsigned less than or equal |
vcle_u32⚠ | Experimentalneon and v7 and ARMCompare unsigned less than or equal |
vcleq_f32⚠ | Experimentalneon and v7 and ARMFloating-point compare less than or equal |
vcleq_s8⚠ | Experimentalneon and v7 and ARMCompare signed less than or equal |
vcleq_s16⚠ | Experimentalneon and v7 and ARMCompare signed less than or equal |
vcleq_s32⚠ | Experimentalneon and v7 and ARMCompare signed less than or equal |
vcleq_u8⚠ | Experimentalneon and v7 and ARMCompare unsigned less than or equal |
vcleq_u16⚠ | Experimentalneon and v7 and ARMCompare unsigned less than or equal |
vcleq_u32⚠ | Experimentalneon and v7 and ARMCompare unsigned less than or equal |
vclt_f32⚠ | Experimentalneon and v7 and ARMFloating-point compare less than |
vclt_s8⚠ | Experimentalneon and v7 and ARMCompare signed less than |
vclt_s16⚠ | Experimentalneon and v7 and ARMCompare signed less than |
vclt_s32⚠ | Experimentalneon and v7 and ARMCompare signed less than |
vclt_u8⚠ | Experimentalneon and v7 and ARMCompare unsigned less than |
vclt_u16⚠ | Experimentalneon and v7 and ARMCompare unsigned less than |
vclt_u32⚠ | Experimentalneon and v7 and ARMCompare unsigned less than |
vcltq_f32⚠ | Experimentalneon and v7 and ARMFloating-point compare less than |
vcltq_s8⚠ | Experimentalneon and v7 and ARMCompare signed less than |
vcltq_s16⚠ | Experimentalneon and v7 and ARMCompare signed less than |
vcltq_s32⚠ | Experimentalneon and v7 and ARMCompare signed less than |
vcltq_u8⚠ | Experimentalneon and v7 and ARMCompare unsigned less than |
vcltq_u16⚠ | Experimentalneon and v7 and ARMCompare unsigned less than |
vcltq_u32⚠ | Experimentalneon and v7 and ARMCompare unsigned less than |
vdupq_n_s8⚠ | Experimentalneon and v7 and ARMDuplicate vector element to vector or scalar |
vdupq_n_u8⚠ | Experimentalneon and v7 and ARMDuplicate vector element to vector or scalar |
veor_s8⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veor_s16⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veor_s32⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veor_s64⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veor_u8⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veor_u16⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veor_u32⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veor_u64⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veorq_s8⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veorq_s16⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veorq_s32⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veorq_s64⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veorq_u8⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veorq_u16⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veorq_u32⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
veorq_u64⚠ | Experimentalneon and v7 and ARMVector bitwise exclusive or (vector) |
vextq_s8⚠ | Experimentalneon and v7 and ARMExtract vector from pair of vectors |
vextq_u8⚠ | Experimentalneon and v7 and ARMExtract vector from pair of vectors |
vget_lane_u8⚠ | Experimentalneon and v7 and ARMMove vector element to general-purpose register |
vget_lane_u64⚠ | Experimentalneon and v7 and ARMMove vector element to general-purpose register |
vgetq_lane_u16⚠ | Experimentalneon and v7 and ARMMove vector element to general-purpose register |
vgetq_lane_u32⚠ | Experimentalneon and v7 and ARMMove vector element to general-purpose register |
vgetq_lane_u64⚠ | Experimentalneon and v7 and ARMMove vector element to general-purpose register |
vhadd_s8⚠ | Experimentalneon and v7 and ARMHalving add |
vhadd_s16⚠ | Experimentalneon and v7 and ARMHalving add |
vhadd_s32⚠ | Experimentalneon and v7 and ARMHalving add |
vhadd_u8⚠ | Experimentalneon and v7 and ARMHalving add |
vhadd_u16⚠ | Experimentalneon and v7 and ARMHalving add |
vhadd_u32⚠ | Experimentalneon and v7 and ARMHalving add |
vhaddq_s8⚠ | Experimentalneon and v7 and ARMHalving add |
vhaddq_s16⚠ | Experimentalneon and v7 and ARMHalving add |
vhaddq_s32⚠ | Experimentalneon and v7 and ARMHalving add |
vhaddq_u8⚠ | Experimentalneon and v7 and ARMHalving add |
vhaddq_u16⚠ | Experimentalneon and v7 and ARMHalving add |
vhaddq_u32⚠ | Experimentalneon and v7 and ARMHalving add |
vhsub_s8⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsub_s16⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsub_s32⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsub_u8⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsub_u16⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsub_u32⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsubq_s8⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsubq_s16⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsubq_s32⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsubq_u8⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsubq_u16⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vhsubq_u32⚠ | Experimentalneon and v7 and ARMSigned halving subtract |
vld1q_s8⚠ | Experimentalneon and v7 and ARMLoad multiple single-element structures to one, two, three, or four registers |
vld1q_u8⚠ | Experimentalneon and v7 and ARMLoad multiple single-element structures to one, two, three, or four registers |
vmovl_s8⚠ | Experimentalneon and v7 and ARMVector long move. |
vmovl_s16⚠ | Experimentalneon and v7 and ARMVector long move. |
vmovl_s32⚠ | Experimentalneon and v7 and ARMVector long move. |
vmovl_u8⚠ | Experimentalneon and v7 and ARMVector long move. |
vmovl_u16⚠ | Experimentalneon and v7 and ARMVector long move. |
vmovl_u32⚠ | Experimentalneon and v7 and ARMVector long move. |
vmovn_s16⚠ | Experimentalneon and v7 and ARMVector narrow integer. |
vmovn_s32⚠ | Experimentalneon and v7 and ARMVector narrow integer. |
vmovn_s64⚠ | Experimentalneon and v7 and ARMVector narrow integer. |
vmovn_u16⚠ | Experimentalneon and v7 and ARMVector narrow integer. |
vmovn_u32⚠ | Experimentalneon and v7 and ARMVector narrow integer. |
vmovn_u64⚠ | Experimentalneon and v7 and ARMVector narrow integer. |
vmovq_n_u8⚠ | Experimentalneon and v7 and ARMDuplicate vector element to vector or scalar |
vmul_f32⚠ | Experimentalneon and v7 and ARMMultiply |
vmul_s8⚠ | Experimentalneon and v7 and ARMMultiply |
vmul_s16⚠ | Experimentalneon and v7 and ARMMultiply |
vmul_s32⚠ | Experimentalneon and v7 and ARMMultiply |
vmul_u8⚠ | Experimentalneon and v7 and ARMMultiply |
vmul_u16⚠ | Experimentalneon and v7 and ARMMultiply |
vmul_u32⚠ | Experimentalneon and v7 and ARMMultiply |
vmulq_f32⚠ | Experimentalneon and v7 and ARMMultiply |
vmulq_s8⚠ | Experimentalneon and v7 and ARMMultiply |
vmulq_s16⚠ | Experimentalneon and v7 and ARMMultiply |
vmulq_s32⚠ | Experimentalneon and v7 and ARMMultiply |
vmulq_u8⚠ | Experimentalneon and v7 and ARMMultiply |
vmulq_u16⚠ | Experimentalneon and v7 and ARMMultiply |
vmulq_u32⚠ | Experimentalneon and v7 and ARMMultiply |
vmvn_p8⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvn_s8⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvn_s16⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvn_s32⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvn_u8⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvn_u16⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvn_u32⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvnq_p8⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvnq_s8⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvnq_s16⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvnq_s32⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvnq_u8⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvnq_u16⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vmvnq_u32⚠ | Experimentalneon and v7 and ARMVector bitwise not. |
vorr_s8⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorr_s16⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorr_s32⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorr_s64⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorr_u8⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorr_u16⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorr_u32⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorr_u64⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorrq_s8⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorrq_s16⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorrq_s32⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorrq_s64⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorrq_u8⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorrq_u16⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorrq_u32⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vorrq_u64⚠ | Experimentalneon and v7 and ARMVector bitwise or (immediate, inclusive) |
vpmax_f32⚠ | Experimentalneon and v7 and ARMFolding maximum of adjacent pairs |
vpmax_s8⚠ | Experimentalneon and v7 and ARMFolding maximum of adjacent pairs |
vpmax_s16⚠ | Experimentalneon and v7 and ARMFolding maximum of adjacent pairs |
vpmax_s32⚠ | Experimentalneon and v7 and ARMFolding maximum of adjacent pairs |
vpmax_u8⚠ | Experimentalneon and v7 and ARMFolding maximum of adjacent pairs |
vpmax_u16⚠ | Experimentalneon and v7 and ARMFolding maximum of adjacent pairs |
vpmax_u32⚠ | Experimentalneon and v7 and ARMFolding maximum of adjacent pairs |
vpmin_f32⚠ | Experimentalneon and v7 and ARMFolding minimum of adjacent pairs |
vpmin_s8⚠ | Experimentalneon and v7 and ARMFolding minimum of adjacent pairs |
vpmin_s16⚠ | Experimentalneon and v7 and ARMFolding minimum of adjacent pairs |
vpmin_s32⚠ | Experimentalneon and v7 and ARMFolding minimum of adjacent pairs |
vpmin_u8⚠ | Experimentalneon and v7 and ARMFolding minimum of adjacent pairs |
vpmin_u16⚠ | Experimentalneon and v7 and ARMFolding minimum of adjacent pairs |
vpmin_u32⚠ | Experimentalneon and v7 and ARMFolding minimum of adjacent pairs |
vqadd_s8⚠ | Experimentalneon and v7 and ARMSaturating add |
vqadd_s16⚠ | Experimentalneon and v7 and ARMSaturating add |
vqadd_s32⚠ | Experimentalneon and v7 and ARMSaturating add |
vqadd_u8⚠ | Experimentalneon and v7 and ARMSaturating add |
vqadd_u16⚠ | Experimentalneon and v7 and ARMSaturating add |
vqadd_u32⚠ | Experimentalneon and v7 and ARMSaturating add |
vqaddq_s8⚠ | Experimentalneon and v7 and ARMSaturating add |
vqaddq_s16⚠ | Experimentalneon and v7 and ARMSaturating add |
vqaddq_s32⚠ | Experimentalneon and v7 and ARMSaturating add |
vqaddq_u8⚠ | Experimentalneon and v7 and ARMSaturating add |
vqaddq_u16⚠ | Experimentalneon and v7 and ARMSaturating add |
vqaddq_u32⚠ | Experimentalneon and v7 and ARMSaturating add |
vqmovn_u64⚠ | Experimentalneon and v7 and ARMUnsigned saturating extract narrow. |
vqsub_s8⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsub_s16⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsub_s32⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsub_u8⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsub_u16⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsub_u32⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsubq_s8⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsubq_s16⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsubq_s32⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsubq_u8⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsubq_u16⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vqsubq_u32⚠ | Experimentalneon and v7 and ARMSaturating subtract |
vreinterpret_u64_u32⚠ | Experimentalneon and v7 and ARMVector reinterpret cast operation |
vreinterpretq_s8_u8⚠ | Experimentalneon and v7 and ARMVector reinterpret cast operation |
vreinterpretq_u16_u8⚠ | Experimentalneon and v7 and ARMVector reinterpret cast operation |
vreinterpretq_u32_u8⚠ | Experimentalneon and v7 and ARMVector reinterpret cast operation |
vreinterpretq_u64_u8⚠ | Experimentalneon and v7 and ARMVector reinterpret cast operation |
vreinterpretq_u8_s8⚠ | Experimentalneon and v7 and ARMVector reinterpret cast operation |
vrhadd_s8⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhadd_s16⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhadd_s32⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhadd_u8⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhadd_u16⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhadd_u32⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhaddq_s8⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhaddq_s16⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhaddq_s32⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhaddq_u8⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhaddq_u16⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrhaddq_u32⚠ | Experimentalneon and v7 and ARMRounding halving add |
vrsqrte_f32⚠ | ExperimentalARM and neon Reciprocal square-root estimate. |
vshlq_n_u8⚠ | Experimentalneon and v7 and ARMShift right |
vshrq_n_u8⚠ | Experimentalneon and v7 and ARMUnsigned shift right |
vsub_f32⚠ | Experimentalneon and v7 and ARMSubtract |
vsub_s8⚠ | Experimentalneon and v7 and ARMSubtract |
vsub_s16⚠ | Experimentalneon and v7 and ARMSubtract |
vsub_s32⚠ | Experimentalneon and v7 and ARMSubtract |
vsub_s64⚠ | Experimentalneon and v7 and ARMSubtract |
vsub_u8⚠ | Experimentalneon and v7 and ARMSubtract |
vsub_u16⚠ | Experimentalneon and v7 and ARMSubtract |
vsub_u32⚠ | Experimentalneon and v7 and ARMSubtract |
vsub_u64⚠ | Experimentalneon and v7 and ARMSubtract |
vsubq_f32⚠ | Experimentalneon and v7 and ARMSubtract |
vsubq_s8⚠ | Experimentalneon and v7 and ARMSubtract |
vsubq_s16⚠ | Experimentalneon and v7 and ARMSubtract |
vsubq_s32⚠ | Experimentalneon and v7 and ARMSubtract |
vsubq_s64⚠ | Experimentalneon and v7 and ARMSubtract |
vsubq_u8⚠ | Experimentalneon and v7 and ARMSubtract |
vsubq_u16⚠ | Experimentalneon and v7 and ARMSubtract |
vsubq_u32⚠ | Experimentalneon and v7 and ARMSubtract |
vsubq_u64⚠ | Experimentalneon and v7 and ARMSubtract |
vtbl1_p8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl1_s8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl1_u8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl2_p8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl2_s8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl2_u8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl3_p8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl3_s8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl3_u8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl4_p8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl4_s8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbl4_u8⚠ | ExperimentalARM and neon,v7 Table look-up |
vtbx1_p8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx1_s8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx1_u8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx2_p8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx2_s8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx2_u8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx3_p8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx3_s8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx3_u8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx4_p8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx4_s8⚠ | ExperimentalARM and neon,v7 Extended table look-up |
vtbx4_u8⚠ | ExperimentalARM and neon,v7 Extended table look-up |