.. 3.10

Clock Divider
=============

**Objective**

Study of a clock divider, using a D flip-flop (TTL family, 7474).

**Procedure**

.. image:: schematics/clock-divider.svg
	   :width: 300px

-  Enable A1 and A2, set range to 8 volts fullscale
-  Set SQ1 to 500 Hz

**Discussion**

The output toggles at every rising edge of the input, resulting in a
division of frequency by two. The output is a symmetric squarewave,
irrespective of the duty cycle of the input pulse. The HIGH output of
the TTL IC is around 4 volts only.

+-------------------------------------------------------------------------+
|.. image:: pics/clock-divider.png                                        |
|	   :width: 300px                                                  |
|.. image:: pics/clock-divider2.png                                       |
|	   :width: 300px                                                  |
+-------------------------------------------------------------------------+
|Figure 3.1 A clock divider circuit, using a D-flipflop. Outputs for two  |
|different types of input are shown                                       |
+-------------------------------------------------------------------------+

