36 #ifndef ARM_TRC_CMP_CFG_PTM_H_INCLUDED 37 #define ARM_TRC_CMP_CFG_PTM_H_INCLUDED 104 const bool hasTS()
const;
105 const bool enaTS()
const;
156 return ((
int)m_cfg.
reg_idr & 0xF0) >> 4;
208 #endif // ARM_TRC_CMP_CFG_PTM_H_INCLUDED const bool TSPkt64() const
timestamp packet is 64 bits in size.
const bool enaCycleAcc() const
cycle accurate tracing enabled.
static const uint32_t CTRL_CYCLEACC
const ocsd_arch_version_t & archVersion() const
const bool enaVMID() const
VMID tracing enabled.
const bool enaTS() const
Timestamp trace is enabled.
static const uint32_t CTRL_VMID_ENA
const int CtxtIDBytes() const
number of context ID bytes traced 1,2,4;
const bool TSBinEnc() const
Timestamp encoded as natural binary number.
const bool dmsbWayPt() const
DMB and DSB are waypoint instructions.
static const uint32_t CCER_TS_IMPL
const bool enaBranchBCast() const
Branch broadcast enabled.
Interpreter class for PTM Hardware configuration.
static const uint32_t CCER_TS_64BIT
const ocsd_core_profile_t & coreProfile() const
static const uint32_t CCER_RESTACK_IMPL
static const uint32_t CCER_VIRTEXT
ocsd_arch_version_t arch_ver
const bool hasRetStack() const
return stack implemented.
static const uint32_t CCER_DMSB_WPT
ocsd_core_profile_t core_prof
static const uint32_t CCER_TS_ENC_NAT
const bool hasVirtExt() const
processor has virtualisation extensions.
Base class for configuration data on CoreSight trace component.
const bool dmsbGenTS() const
TS generated for DMB and DSB.
const bool enaRetStack() const
return stack enabled.
PtmConfig & operator=(const ocsd_ptm_cfg *p_cfg)
copy assignment operator for base structure into class.
static const uint32_t CCER_TS_DMSB
const bool hasTS() const
Timestamps implemented in trace.
virtual const uint8_t getTraceID() const
CoreSight Trace ID for this device.
static const uint32_t CTRL_BRANCH_BCAST
const int MinorRev() const
return X revision in 1.X
static const uint32_t CTRL_TS_ENA
static const uint32_t CTRL_RETSTACK_ENA