36 #ifndef ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED 37 #define ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED 114 const uint32_t
cidSize()
const;
116 const uint32_t
daSize()
const;
117 const uint32_t
dvSize()
const;
118 const uint32_t
ccSize()
const;
175 QSuppType m_QSuppType;
180 bool m_condTraceCalc;
181 CondITrace_t m_CondTrace;
189 return (
bool)((m_cfg.
reg_idr0 & 0x6) == 0x6);
194 return (
bool)((m_cfg.
reg_idr0 & 0x18) == 0x18);
199 return (
bool)((m_cfg.
reg_idr0 & 0x20) == 0x20);
204 return (
bool)((m_cfg.
reg_idr0 & 0x40) == 0x40);
209 return (
bool)((m_cfg.
reg_idr0 & 0x80) == 0x80);
214 return (
bool)((m_cfg.
reg_idr0 & 0x200) == 0x200);
219 return ((m_cfg.
reg_idr0 >> 10) & 0x3) + 1;
229 if(!m_QSuppCalc) CalcQSupp();
235 if(!m_QSuppCalc) CalcQSupp();
236 return (
bool)(m_QSuppType !=
Q_NONE);
241 if(!m_QSuppCalc) CalcQSupp();
242 return m_QSuppFilter;
247 return (
bool)((m_cfg.
reg_idr0 & 0x20000) == 0x20000);
252 uint32_t tsSizeF = (m_cfg.
reg_idr0 >> 24) & 0x1F;
268 return (uint8_t)((m_cfg.
reg_idr1 >> 8) & 0xF);
273 return (uint8_t)((m_cfg.
reg_idr1 >> 4) & 0xF);
280 return ((m_cfg.
reg_idr2 & 0x1F) == 0x8) ? 64 : 32;
285 return (((m_cfg.
reg_idr2 >> 5) & 0x1F) == 0x4) ? 32 : 0;
299 uint32_t daSizeF = ((m_cfg.
reg_idr2 >> 15) & 0x1F);
301 return (((m_cfg.
reg_idr2 >> 15) & 0x1F) == 0x8) ? 64 : 32;
307 uint32_t dvSizeF = ((m_cfg.
reg_idr2 >> 20) & 0x1F);
309 return (((m_cfg.
reg_idr2 >> 20) & 0x1F) == 0x8) ? 64 : 32;
315 return ((m_cfg.
reg_idr2 >> 25) & 0xF) + 12;
424 m_condTraceCalc =
true;
447 #endif // ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
const uint32_t MaxSpecDepth() const
Interpreter class for etm v4 config structure.
const bool hasTrcExcpData() const
const uint32_t cidSize() const
enum EtmV4Config::_condType condType
const uint32_t ccSize() const
const bool hasRetStack() const
const ocsd_core_profile_t & coreProfile() const
const uint32_t P1_Spcl_Key_Max() const
EtmV4Config & operator=(const ocsd_etmv4_cfg *p_cfg)
copy assignment operator for base structure into class.
virtual const uint8_t getTraceID() const
CoreSight Trace ID for this device.
const bool commitOpt1() const
const LSP0_t LSP0Type() const
const uint32_t CondKeyMax() const
ocsd_core_profile_t core_prof
const bool enabledBrBroad() const
const bool enabledCCI() const
const condType hasCondType() const
const bool hasCondTrace() const
const bool vmidOpt() const
const uint32_t TimeStampSize() const
const uint32_t iaSizeMax() const
const bool enabledDataTrace() const
const uint32_t CondKeyMaxIncr() const
const QSuppType getQSuppType()
const bool hasDataTrace() const
const bool enabledLSP0Trace() const
const CondITrace_t enabledCondITrace()
const uint32_t vmidSize()
const bool enabledCID() const
const uint8_t MinVersion() const
const uint32_t daSize() const
const uint8_t numEvents() const
Base class for configuration data on CoreSight trace component.
const bool enabledVMID() const
const bool enabledQE() const
enum EtmV4Config::_QSuppType QSuppType
const bool enabledRetStack() const
const uint32_t dvSize() const
const uint32_t P1_Key_Max() const
const ocsd_arch_version_t & archVersion() const
const uint32_t CondSpecKeyMax() const
const bool enabledDATrace() const
const uint8_t MajVersion() const
const bool hasCycleCountI() const
const uint32_t P0_Key_Max() const
const bool enabledTS() const
const bool hasBranchBroadcast() const
const bool enabledDVTrace() const
const bool LSasInstP0() const
ocsd_arch_version_t arch_ver