Device tree bindings for OMAP general purpose memory controllers (GPMC)

The actual devices are instantiated from the child nodes of a GPMC node.

Required properties:

 - compatible:		Should be set to one of the following:

			ti,omap2420-gpmc (omap2420)
			ti,omap2430-gpmc (omap2430)
			ti,omap3430-gpmc (omap3430 & omap3630)
			ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
			ti,am3352-gpmc   (am335x devices)

 - reg:			A resource specifier for the register space
			(see the example below)
 - ti,hwmods:		Should be set to "ti,gpmc" until the DT transition is
			completed.
 - #address-cells:	Must be set to 2 to allow memory address translation
 - #size-cells:		Must be set to 1 to allow CS address passing
 - gpmc,num-cs:		The maximum number of chip-select lines that controller
			can support.
 - gpmc,num-waitpins:	The maximum number of wait pins that controller can
			support.
 - ranges:		Must be set up to reflect the memory layout with four
			integer values for each chip-select line in use:

			   <cs-number> 0 <physical address of mapping> <size>

			Currently, calculated values derived from the contents
			of the per-CS register GPMC_CONFIG7 (as set up by the
			bootloader) are used for the physical address decoding.
			As this will change in the future, filling correct
			values here is a requirement.
 - interrupt-controller: The GPMC driver implements and interrupt controller for
			the NAND events "fifoevent" and "termcount" plus the
			rising/falling edges on the GPMC_WAIT pins.
			The interrupt number mapping is as follows
			0 - NAND_fifoevent
			1 - NAND_termcount
			2 - GPMC_WAIT0 pin edge
			3 - GPMC_WAIT1 pin edge, and so on.
 - interrupt-cells:	Must be set to 2
 - gpio-controller:	The GPMC driver implements a GPIO controller for the
			GPMC WAIT pins that can be used as general purpose inputs.
			0 maps to GPMC_WAIT0 pin.
 - gpio-cells:		Must be set to 2

Timing properties for child nodes. All are optional and default to 0.

 - gpmc,sync-clk-ps:	Minimum clock period for synchronous mode, in picoseconds

 Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
 - gpmc,cs-on-ns:	Assertion time
 - gpmc,cs-rd-off-ns:	Read deassertion time
 - gpmc,cs-wr-off-ns:	Write deassertion time

 ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
 - gpmc,adv-on-ns:	Assertion time
 - gpmc,adv-rd-off-ns:	Read deassertion time
 - gpmc,adv-wr-off-ns:	Write deassertion time
 - gpmc,adv-aad-mux-on-ns:	Assertion time for AAD
 - gpmc,adv-aad-mux-rd-off-ns:	Read deassertion time for AAD
 - gpmc,adv-aad-mux-wr-off-ns:	Write deassertion time for AAD

 WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
 - gpmc,we-on-ns	Assertion time
 - gpmc,we-off-ns:	Deassertion time

 OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
 - gpmc,oe-on-ns:	Assertion time
 - gpmc,oe-off-ns:	Deassertion time
 - gpmc,oe-aad-mux-on-ns:	Assertion time for AAD
 - gpmc,oe-aad-mux-off-ns:	Deassertion time for AAD

 Access time and cycle time timings (in nanoseconds) corresponding to
 GPMC_CONFIG5:
 - gpmc,page-burst-access-ns: 	Multiple access word delay
 - gpmc,access-ns:		Start-cycle to first data valid delay
 - gpmc,rd-cycle-ns:		Total read cycle time
 - gpmc,wr-cycle-ns:		Total write cycle time
 - gpmc,bus-turnaround-ns:	Turn-around time between successive accesses
 - gpmc,cycle2cycle-delay-ns:	Delay between chip-select pulses
 - gpmc,clk-activation-ns: 	GPMC clock activation time
 - gpmc,wait-monitoring-ns:	Start of wait monitoring with regard to valid
				data

Boolean timing parameters. If property is present parameter enabled and
disabled if omitted:
 - gpmc,adv-extra-delay:	ADV signal is delayed by half GPMC clock
 - gpmc,cs-extra-delay:		CS signal is delayed by half GPMC clock
 - gpmc,cycle2cycle-diffcsen:	Add "cycle2cycle-delay" between successive
				accesses to a different CS
 - gpmc,cycle2cycle-samecsen:	Add "cycle2cycle-delay" between successive
				accesses to the same CS
 - gpmc,oe-extra-delay:		OE signal is delayed by half GPMC clock
 - gpmc,we-extra-delay:		WE signal is delayed by half GPMC clock
 - gpmc,time-para-granularity:	Multiply all access times by 2

The following are only applicable to OMAP3+ and AM335x:
 - gpmc,wr-access-ns:		In synchronous write mode, for single or
				burst accesses, defines the number of
				GPMC_FCLK cycles from start access time
				to the GPMC_CLK rising edge used by the
				memory device for the first data capture.
 - gpmc,wr-data-mux-bus-ns:	In address-data multiplex mode, specifies
				the time when the first data is driven on
				the address-data bus.

GPMC chip-select settings properties for child nodes. All are optional.

- gpmc,burst-length	Page/burst length. Must be 4, 8 or 16.
- gpmc,burst-wrap	Enables wrap bursting
- gpmc,burst-read	Enables read page/burst mode
- gpmc,burst-write	Enables write page/burst mode
- gpmc,device-width	Total width of device(s) connected to a GPMC
			chip-select in bytes. The GPMC supports 8-bit
			and 16-bit devices and so this property must be
			1 or 2.
- gpmc,mux-add-data	Address and data multiplexing configuration.
			Valid values are 1 for address-address-data
			multiplexing mode and 2 for address-data
			multiplexing mode.
- gpmc,sync-read	Enables synchronous read. Defaults to asynchronous
			is this is not set.
- gpmc,sync-write	Enables synchronous writes. Defaults to asynchronous
			is this is not set.
- gpmc,wait-pin		Wait-pin used by client. Must be less than
			"gpmc,num-waitpins".
- gpmc,wait-on-read	Enables wait monitoring on reads.
- gpmc,wait-on-write	Enables wait monitoring on writes.

Example for an AM33xx board:

	gpmc: gpmc@50000000 {
		compatible = "ti,am3352-gpmc";
		ti,hwmods = "gpmc";
		reg = <0x50000000 0x2000>;
		interrupts = <100>;

		gpmc,num-cs = <8>;
		gpmc,num-waitpins = <2>;
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;

		/* child nodes go here */
	};
