--- a/sys/mips/malta/gt_pci.c
+++ b/sys/mips/malta/gt_pci.c
@@ -59,6 +59,7 @@
 #include <machine/bus.h>
 #include <machine/cpu.h>
 #include <machine/pmap.h>
+#include <machine/timerreg.h>
 
 #include <mips/malta/maltareg.h>
 
@@ -401,7 +402,42 @@
 	}
 
 	/* Initialize memory and i/o rmans. */
-	device_add_child(dev, "pci", busno);
+	{
+		device_t child;
+		int rid;
+		void *res;
+
+		child = device_add_child(dev, "pci", busno);
+
+		res = bus_alloc_resource(child, SYS_RES_IOPORT, &rid, IO_ICU1, IO_ICU1 + IO_ICUSIZE, IO_ICUSIZE, RF_ACTIVE);
+		if (res == NULL)
+			device_printf(child, "cannot allocate registers for i8259 controller #1\n");
+
+		res = bus_alloc_resource(child, SYS_RES_IOPORT, &rid, IO_ICU2, IO_ICU2 + IO_ICUSIZE, IO_ICUSIZE, RF_ACTIVE);
+		if (res == NULL)
+			device_printf(child, "cannot allocate registers for i8259 controller #2\n");
+
+		res = bus_alloc_resource(child, SYS_RES_IOPORT, &rid, IO_TIMER1, IO_TIMER1 + IO_TIMERSIZE, IO_TIMERSIZE, RF_ACTIVE);
+		if (res == NULL)
+			device_printf(child, "cannot allocate registers for i8254 controllers\n");
+
+		res = bus_alloc_resource(child, SYS_RES_IOPORT, &rid, MALTA_SMSC_KYBD_ADR, MALTA_SMSC_KYBD_ADR + 1, 1, RF_ACTIVE);
+		if (res == NULL)
+			device_printf(child, "cannot allocate registers for keyboard controller\n");
+
+		res = bus_alloc_resource(child, SYS_RES_IOPORT, &rid, MALTA_SMSC_KYBD_ADR + 4, MALTA_SMSC_KYBD_ADR + 4 + 1, 1, RF_ACTIVE);
+		if (res == NULL)
+			device_printf(child, "cannot allocate registers for keyboard controller\n");
+
+		res = bus_alloc_resource(child, SYS_RES_IOPORT, &rid, MALTA_RTCADR, MALTA_RTCADR + 2, 2, RF_ACTIVE);
+		if (res == NULL)
+			device_printf(child, "cannot allocate registers for RTC controller\n");
+
+		res = bus_alloc_resource(child, SYS_RES_IOPORT, &rid, 0x81, 0x81 + 1, 1, RF_ACTIVE);
+		if (res == NULL)
+			device_printf(child, "cannot allocate registers for DMA controller\n");
+	}
+
 	return (bus_generic_attach(dev));
 }
 
--- a/sys/mips/include/timerreg.h
+++ b/sys/mips/include/timerreg.h
@@ -49,6 +49,9 @@
 #define	TIMER_CNTR2	(IO_TIMER1 + TIMER_REG_CNTR2)
 #define	TIMER_MODE	(IO_TIMER1 + TIMER_REG_MODE)
 
+/* 3 timers, 4 registers each. */
+#define IO_TIMERSIZE	3 * 4
+
 #define	timer_spkr_acquire() \
 	acquire_timer2(TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT)
 #define	timer_spkr_release() \