CHANGE LOG for Xilinx LogiCORE Fast Fourier Transform 8.0

Release Date:  December 18, 2012
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Table of Contents

1.   INTRODUCTION
2.   DEVICE SUPPORT
3.   NEW FEATURE HISTORY
4.   RESOLVED ISSUES
5.   KNOWN ISSUES & LIMITATIONS
6.   TECHNICAL SUPPORT & FEEDBACK
7.   CORE RELEASE HISTORY
8.   LEGAL DISCLAIMER

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1. INTRODUCTION

  This file contains the change log for all released versions of the Xilinx
  LogiCORE IP Fast Fourier Transform.

  For the latest core updates, see the product page at:

    http://www.xilinx.com/products/ipcenter/FFT.htm

  For installation instructions for this release, please go to:

    http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

  For system requirements:

    http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm


2. DEVICE SUPPORT

  2.1. ISE

    The following device families are supported by the core for this release:

    All Series 7 devices
    All Virtex-6 devices
    All Spartan-6 devices

  2.2. VIVADO

    The following device families are supported by the core for this release:

    All Series 7 devices


3. NEW FEATURE HISTORY

  3.1 ISE

  v8.0
    - Ongoing new device support.
    - AXI4-Stream Interfaces replace old pinout
    - C model available in CORE Generator in 14.1

  3.1 VIVADO

  v8.0
    - Introduction to Vivado.
    - Same features as for ISE.


4. RESOLVED ISSUES

  4.1 ISE

  v8.0
    1. C model LSB mismatch for odd point sizes, streaming architecture
      - CR546238
      - CR576743
      - CR576806

    2. Tooltip for ARESETN did not indicate active low.
      - CR572366


  4.2 Vivado

    - N/A


5. KNOWN ISSUES & LIMITATIONS

  The following are known issues for this core at time of release:

  5.1 ISE
    1. The core will drop data sent within 2 cycles of the disassertion
       of ARESETN. The workaround is to ensure no transfers are
       attempted for 2 clock cycles following the release of ARESETN.
       - CR 591111.

    2. The bit-accurate C model and Matlab MEX function for the FFT core
       can return incorrect results when configured to perform a Block
       Floating-Point FFT using the Pipelined, Streaming I/O architecture.
      - CR 639407
      - AR 53087


  5.2 Vivado
    1. Core may fail to compile in XSIM.
       - CR667416
       - AR50923

    2. As per 2 in ISE section.

  For a comprehensive listing of Known Issues for this core, please see the IP
  Release Notes Guide,

    www.xilinx.com/support/documentation/user_guides/xtp025.pdf


6. TECHNICAL SUPPORT & FEEDBACK

  To obtain technical support, create a WebCase at www.xilinx.com/support.
  Questions are routed to a team with expertise using this product.
  Please feel free to leave feedback on this IP under the "Leave Feedback"
  menu item in Vivado/PlanAhead.

  Xilinx provides technical support for use of this product when used
  according to the guidelines described in the core documentation, and
  cannot guarantee timing, functionality, or support of this product for
  designs that do not follow specified guidelines.


7. CORE RELEASE HISTORY

Date        By            Version      Description
================================================================================
12/18/2012  Xilinx, Inc.  8.0         ISE 14.4 and Vivado 2012.4 support
10/16/2012  Xilinx, Inc.  8.0         ISE 14.3 and Vivado 2012.3 support
07/25/2012  Xilinx, Inc.  8.0         ISE 14.2 and Vivado 2012.2 support
04/24/2012  Xilinx, Inc.  8.0         ISE 14.1 support and Vivado 2012.1 support,
                                      C model in CORE Generator
01/11/2012  Xilinx, Inc.  8.0         ISE 13.4 support
10/19/2011  Xilinx, Inc.  8.0         ISE 13.3 support
06/22/2011  Xilinx, Inc.  8.0         ISE 13.2 support, Artix-7 support
03/01/2011  Xilinx, Inc.  8.0         ISE 13.1 support, Virtex-7 and Kintex-7 support
09/21/2010  Xilinx, Inc.  8.0         ISE 12.3 support. AXI4-Streaming.
04/19/2010  Xilinx, Inc.  7.1         ISE 12.1 support. Bugfixes.
12/02/2009  Xilinx, Inc.  7.0         ISE 11.4 support, Spartan-6L support.
09/16/2009  Xilinx, Inc.  7.0         ISE 11.3 support, Virtex-6L support.
06/24/2009  Xilinx, Inc.  7.0         ISE 11.2 support, Virtex-6/Spartan-6 support.
09/19/2008  Xilinx, Inc.  6.0         ISE 10.1 support. Features added. Bugfixes.
10/10/2007  Xilinx, Inc.  5.0         ISE 9.2i support. Features added. Bugfixes.
================================================================================


8. LEGAL DISCLAIMER

  (c) Copyright 2000 - 2012 Xilinx, Inc. All rights reserved.

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  of Xilinx, Inc. and is protected under U.S. and
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