34 #ifndef _RTE_ETH_CTRL_H_ 35 #define _RTE_ETH_CTRL_H_ 63 #define RTE_ETH_FLOW_UNKNOWN 0 64 #define RTE_ETH_FLOW_RAW 1 65 #define RTE_ETH_FLOW_IPV4 2 66 #define RTE_ETH_FLOW_FRAG_IPV4 3 67 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4 68 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5 69 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6 70 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7 71 #define RTE_ETH_FLOW_IPV6 8 72 #define RTE_ETH_FLOW_FRAG_IPV6 9 73 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10 74 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11 75 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12 76 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13 77 #define RTE_ETH_FLOW_L2_PAYLOAD 14 78 #define RTE_ETH_FLOW_IPV6_EX 15 79 #define RTE_ETH_FLOW_IPV6_TCP_EX 16 80 #define RTE_ETH_FLOW_IPV6_UDP_EX 17 81 #define RTE_ETH_FLOW_PORT 18 83 #define RTE_ETH_FLOW_VXLAN 19 84 #define RTE_ETH_FLOW_GENEVE 20 85 #define RTE_ETH_FLOW_NVGRE 21 86 #define RTE_ETH_FLOW_MAX 22 92 RTE_ETH_FILTER_NONE = 0,
93 RTE_ETH_FILTER_MACVLAN,
94 RTE_ETH_FILTER_ETHERTYPE,
95 RTE_ETH_FILTER_FLEXIBLE,
97 RTE_ETH_FILTER_NTUPLE,
98 RTE_ETH_FILTER_TUNNEL,
101 RTE_ETH_FILTER_L2_TUNNEL,
119 RTE_ETH_FILTER_OP_MAX
147 #define RTE_ETHTYPE_FLAGS_MAC 0x0001 148 #define RTE_ETHTYPE_FLAGS_DROP 0x0002 155 struct rte_eth_ethertype_filter { 162 #define RTE_FLEX_FILTER_MAXLEN 128 163 #define RTE_FLEX_FILTER_MASK_SIZE \ 164 (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT) 196 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001 197 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002 198 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004 199 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008 200 #define RTE_NTUPLE_FLAGS_PROTO 0x0010 201 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020 203 #define RTE_5TUPLE_FLAGS ( \ 204 RTE_NTUPLE_FLAGS_DST_IP | \ 205 RTE_NTUPLE_FLAGS_SRC_IP | \ 206 RTE_NTUPLE_FLAGS_DST_PORT | \ 207 RTE_NTUPLE_FLAGS_SRC_PORT | \ 208 RTE_NTUPLE_FLAGS_PROTO) 210 #define RTE_2TUPLE_FLAGS ( \ 211 RTE_NTUPLE_FLAGS_DST_PORT | \ 212 RTE_NTUPLE_FLAGS_PROTO) 214 #define TCP_URG_FLAG 0x20 215 #define TCP_ACK_FLAG 0x10 216 #define TCP_PSH_FLAG 0x08 217 #define TCP_RST_FLAG 0x04 218 #define TCP_SYN_FLAG 0x02 219 #define TCP_FIN_FLAG 0x01 220 #define TCP_FLAG_ALL 0x3F 252 RTE_TUNNEL_TYPE_NONE = 0,
253 RTE_TUNNEL_TYPE_VXLAN,
254 RTE_TUNNEL_TYPE_GENEVE,
255 RTE_TUNNEL_TYPE_TEREDO,
256 RTE_TUNNEL_TYPE_NVGRE,
257 RTE_TUNNEL_TYPE_IP_IN_GRE,
258 RTE_L2_TUNNEL_TYPE_E_TAG,
265 #define ETH_TUNNEL_FILTER_OMAC 0x01 266 #define ETH_TUNNEL_FILTER_OIP 0x02 267 #define ETH_TUNNEL_FILTER_TENID 0x04 268 #define ETH_TUNNEL_FILTER_IMAC 0x08 269 #define ETH_TUNNEL_FILTER_IVLAN 0x10 270 #define ETH_TUNNEL_FILTER_IIP 0x20 272 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \ 273 ETH_TUNNEL_FILTER_IVLAN) 274 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \ 275 ETH_TUNNEL_FILTER_IVLAN | \ 276 ETH_TUNNEL_FILTER_TENID) 277 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \ 278 ETH_TUNNEL_FILTER_TENID) 279 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \ 280 ETH_TUNNEL_FILTER_TENID | \ 281 ETH_TUNNEL_FILTER_IMAC) 304 uint32_t ipv6_addr[4];
317 RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
318 RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
319 RTE_ETH_GLOBAL_CFG_TYPE_MAX,
333 #define RTE_ETH_FDIR_MAX_FLEXLEN 16 334 #define RTE_ETH_INSET_SIZE_MAX 128 339 enum rte_eth_input_set_field { 340 RTE_ETH_INPUT_SET_UNKNOWN = 0,
343 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
344 RTE_ETH_INPUT_SET_L2_DST_MAC,
345 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
346 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
347 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
350 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
351 RTE_ETH_INPUT_SET_L3_DST_IP4,
352 RTE_ETH_INPUT_SET_L3_SRC_IP6,
353 RTE_ETH_INPUT_SET_L3_DST_IP6,
354 RTE_ETH_INPUT_SET_L3_IP4_TOS,
355 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
356 RTE_ETH_INPUT_SET_L3_IP6_TC,
357 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
358 RTE_ETH_INPUT_SET_L3_IP4_TTL,
359 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
362 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
363 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
364 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
365 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
366 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
367 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
368 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
371 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
372 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
373 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
374 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
375 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
378 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
379 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
380 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
381 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
382 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
383 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
384 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
385 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
387 RTE_ETH_INPUT_SET_DEFAULT = 65533,
388 RTE_ETH_INPUT_SET_NONE = 65534,
389 RTE_ETH_INPUT_SET_MAX = 65535,
396 RTE_ETH_INPUT_SET_OP_UNKNOWN,
399 RTE_ETH_INPUT_SET_OP_MAX
510 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
511 RTE_FDIR_TUNNEL_TYPE_NVGRE,
512 RTE_FDIR_TUNNEL_TYPE_VXLAN,
570 RTE_ETH_FDIR_ACCEPT = 0,
572 RTE_ETH_FDIR_PASSTHRU,
638 RTE_ETH_PAYLOAD_UNKNOWN = 0,
643 RTE_ETH_PAYLOAD_MAX = 8,
693 #define UINT32_BIT (CHAR_BIT * sizeof(uint32_t)) 694 #define RTE_FLOW_MASK_ARRAY_SIZE \ 695 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) 712 uint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
754 RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
757 RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
784 RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
791 RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
798 RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
801 RTE_ETH_HASH_FUNCTION_MAX,
804 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \ 805 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) 818 uint32_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
820 uint32_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
#define RTE_ETH_FDIR_MAX_FLEXLEN
uint32_t flex_payload_unit
rte_eth_fdir_filter_info_type
#define RTE_FLEX_FILTER_MAXLEN
uint32_t max_flex_payload_segment_num
uint32_t max_flex_bitmask_num
uint32_t flex_bitmask_unit
enum rte_mac_filter_type filter_type
uint16_t flex_payload_limit
#define RTE_ETH_INSET_SIZE_MAX
uint8_t mac_addr_byte_mask
#define RTE_FLEX_FILTER_MASK_SIZE
rte_eth_hash_filter_info_type