SHORT Data cache miss rate/ratio

EVENTSET
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
PMC0  L1D_REPL

METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz]  1.E-06*(FIXC1/FIXC2)/inverseClock
CPI  FIXC1/FIXC0
data cache misses PMC0
data cache miss rate PMC0/FIXC0

LONG
Formulas:
data cache misses = L1D_REPL
data cache miss rate = L1D_REPL / INSTR_RETIRED_ANY
-
This group measures the locality of your data accesses with regard to the L1
cache. The data cache miss rate gives a measure how often it was necessary to
get cache lines from higher levels of the memory hierarchy.

