SHORT L3 cache miss rate/ratio

EVENTSET
PMC0  INSTRUCTIONS_RETIRED
PMC1  L3_READ_REQUEST_ALL_ALL_CORES
PMC2  L3_MISSES_ALL_ALL_CORES

METRICS
Runtime (RDTSC) [s] time
L3 request rate  PMC1/PMC0
L3 miss rate   PMC2/PMC0
L3 miss ratio  PMC2/PMC1

LONG
Formulas:
L3 request rate =  L3_READ_REQUEST_ALL_ALL_CORES/INSTRUCTIONS_RETIRED
L3 miss rate = L3_MISSES_ALL_ALL_CORES/INSTRUCTIONS_RETIRED
L3 miss ratio =  L3_MISSES_ALL_ALL_CORES/L3_READ_REQUEST_ALL_ALL_CORES
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This group measures the locality of your data accesses with regard to the
L3 cache. L3 request rate tells you how data intensive your code is
or how many data accesses you have on average per instruction.
The L3 miss rate gives a measure how often it was necessary to get
cache lines from memory. And finally L3 miss ratio tells you how many of your
memory references required a cache line to be loaded from a higher level.
While the# data cache miss rate might be given by your algorithm you should
try to get data cache miss ratio as low as possible by increasing your cache reuse.
Note: As this group measures the accesses from all cores it only makes sense
to measure with one core per socket, similar as with the Intel Nehalem Uncore events.
This group was taken from the whitepaper -Basic Performance Measurements for AMD Athlon 64,
AMD Opteron and AMD Phenom Processors- from Paul J. Drongowski.


