Eigen  3.2.91
NEON/PacketMath.h
1 // This file is part of Eigen, a lightweight C++ template library
2 // for linear algebra.
3 //
4 // Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>
5 // Copyright (C) 2010 Konstantinos Margaritis <markos@codex.gr>
6 // Heavily based on Gael's SSE version.
7 //
8 // This Source Code Form is subject to the terms of the Mozilla
9 // Public License v. 2.0. If a copy of the MPL was not distributed
10 // with this file, You can obtain one at http://mozilla.org/MPL/2.0/.
11 
12 #ifndef EIGEN_PACKET_MATH_NEON_H
13 #define EIGEN_PACKET_MATH_NEON_H
14 
15 namespace Eigen {
16 
17 namespace internal {
18 
19 #ifndef EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD
20 #define EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 8
21 #endif
22 
23 #ifndef EIGEN_HAS_SINGLE_INSTRUCTION_MADD
24 #define EIGEN_HAS_SINGLE_INSTRUCTION_MADD
25 #endif
26 
27 #ifndef EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD
28 #define EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD
29 #endif
30 
31 // FIXME NEON has 16 quad registers, but since the current register allocator
32 // is so bad, it is much better to reduce it to 8
33 #ifndef EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS
34 #define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS 16
35 #endif
36 
37 typedef float32x2_t Packet2f;
38 typedef float32x4_t Packet4f;
39 typedef int32x4_t Packet4i;
40 typedef int32x2_t Packet2i;
41 typedef uint32x4_t Packet4ui;
42 
43 #define _EIGEN_DECLARE_CONST_Packet4f(NAME,X) \
44  const Packet4f p4f_##NAME = pset1<Packet4f>(X)
45 
46 #define _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(NAME,X) \
47  const Packet4f p4f_##NAME = vreinterpretq_f32_u32(pset1<int>(X))
48 
49 #define _EIGEN_DECLARE_CONST_Packet4i(NAME,X) \
50  const Packet4i p4i_##NAME = pset1<Packet4i>(X)
51 
52 #if EIGEN_COMP_LLVM && !EIGEN_COMP_CLANG
53  //Special treatment for Apple's llvm-gcc, its NEON packet types are unions
54  #define EIGEN_INIT_NEON_PACKET2(X, Y) {{X, Y}}
55  #define EIGEN_INIT_NEON_PACKET4(X, Y, Z, W) {{X, Y, Z, W}}
56 #else
57  //Default initializer for packets
58  #define EIGEN_INIT_NEON_PACKET2(X, Y) {X, Y}
59  #define EIGEN_INIT_NEON_PACKET4(X, Y, Z, W) {X, Y, Z, W}
60 #endif
61 
62 
63 // arm64 does have the pld instruction. If available, let's trust the __builtin_prefetch built-in function
64 // which available on LLVM and GCC (at least)
65 #if EIGEN_HAS_BUILTIN(__builtin_prefetch) || EIGEN_COMP_GNUC
66  #define EIGEN_ARM_PREFETCH(ADDR) __builtin_prefetch(ADDR);
67 #elif defined __pld
68  #define EIGEN_ARM_PREFETCH(ADDR) __pld(ADDR)
69 #elif !EIGEN_ARCH_ARM64
70  #define EIGEN_ARM_PREFETCH(ADDR) __asm__ __volatile__ ( " pld [%[addr]]\n" :: [addr] "r" (ADDR) : "cc" );
71 #else
72  // by default no explicit prefetching
73  #define EIGEN_ARM_PREFETCH(ADDR)
74 #endif
75 
76 template<> struct packet_traits<float> : default_packet_traits
77 {
78  typedef Packet4f type;
79  typedef Packet4f half; // Packet2f intrinsics not implemented yet
80  enum {
81  Vectorizable = 1,
82  AlignedOnScalar = 1,
83  size = 4,
84  HasHalfPacket=0, // Packet2f intrinsics not implemented yet
85 
86  HasDiv = 1,
87  // FIXME check the Has*
88  HasSin = 0,
89  HasCos = 0,
90  HasLog = 0,
91  HasExp = 1,
92  HasSqrt = 0
93  };
94 };
95 template<> struct packet_traits<int> : default_packet_traits
96 {
97  typedef Packet4i type;
98  typedef Packet4i half; // Packet2i intrinsics not implemented yet
99  enum {
100  Vectorizable = 1,
101  AlignedOnScalar = 1,
102  size=4,
103  HasHalfPacket=0 // Packet2i intrinsics not implemented yet
104  // FIXME check the Has*
105  };
106 };
107 
108 #if EIGEN_GNUC_AT_MOST(4,4) && !EIGEN_COMP_LLVM
109 // workaround gcc 4.2, 4.3 and 4.4 compilatin issue
110 EIGEN_STRONG_INLINE float32x4_t vld1q_f32(const float* x) { return ::vld1q_f32((const float32_t*)x); }
111 EIGEN_STRONG_INLINE float32x2_t vld1_f32 (const float* x) { return ::vld1_f32 ((const float32_t*)x); }
112 EIGEN_STRONG_INLINE float32x2_t vld1_dup_f32 (const float* x) { return ::vld1_dup_f32 ((const float32_t*)x); }
113 EIGEN_STRONG_INLINE void vst1q_f32(float* to, float32x4_t from) { ::vst1q_f32((float32_t*)to,from); }
114 EIGEN_STRONG_INLINE void vst1_f32 (float* to, float32x2_t from) { ::vst1_f32 ((float32_t*)to,from); }
115 #endif
116 
117 template<> struct unpacket_traits<Packet4f> { typedef float type; enum {size=4, alignment=Aligned16}; typedef Packet4f half; };
118 template<> struct unpacket_traits<Packet4i> { typedef int type; enum {size=4, alignment=Aligned16}; typedef Packet4i half; };
119 
120 template<> EIGEN_STRONG_INLINE Packet4f pset1<Packet4f>(const float& from) { return vdupq_n_f32(from); }
121 template<> EIGEN_STRONG_INLINE Packet4i pset1<Packet4i>(const int& from) { return vdupq_n_s32(from); }
122 
123 template<> EIGEN_STRONG_INLINE Packet4f plset<Packet4f>(const float& a)
124 {
125  Packet4f countdown = EIGEN_INIT_NEON_PACKET4(0, 1, 2, 3);
126  return vaddq_f32(pset1<Packet4f>(a), countdown);
127 }
128 template<> EIGEN_STRONG_INLINE Packet4i plset<Packet4i>(const int& a)
129 {
130  Packet4i countdown = EIGEN_INIT_NEON_PACKET4(0, 1, 2, 3);
131  return vaddq_s32(pset1<Packet4i>(a), countdown);
132 }
133 
134 template<> EIGEN_STRONG_INLINE Packet4f padd<Packet4f>(const Packet4f& a, const Packet4f& b) { return vaddq_f32(a,b); }
135 template<> EIGEN_STRONG_INLINE Packet4i padd<Packet4i>(const Packet4i& a, const Packet4i& b) { return vaddq_s32(a,b); }
136 
137 template<> EIGEN_STRONG_INLINE Packet4f psub<Packet4f>(const Packet4f& a, const Packet4f& b) { return vsubq_f32(a,b); }
138 template<> EIGEN_STRONG_INLINE Packet4i psub<Packet4i>(const Packet4i& a, const Packet4i& b) { return vsubq_s32(a,b); }
139 
140 template<> EIGEN_STRONG_INLINE Packet4f pnegate(const Packet4f& a) { return vnegq_f32(a); }
141 template<> EIGEN_STRONG_INLINE Packet4i pnegate(const Packet4i& a) { return vnegq_s32(a); }
142 
143 template<> EIGEN_STRONG_INLINE Packet4f pconj(const Packet4f& a) { return a; }
144 template<> EIGEN_STRONG_INLINE Packet4i pconj(const Packet4i& a) { return a; }
145 
146 template<> EIGEN_STRONG_INLINE Packet4f pmul<Packet4f>(const Packet4f& a, const Packet4f& b) { return vmulq_f32(a,b); }
147 template<> EIGEN_STRONG_INLINE Packet4i pmul<Packet4i>(const Packet4i& a, const Packet4i& b) { return vmulq_s32(a,b); }
148 
149 template<> EIGEN_STRONG_INLINE Packet4f pdiv<Packet4f>(const Packet4f& a, const Packet4f& b)
150 {
151 #if EIGEN_ARCH_ARM64
152  return vdivq_f32(a,b);
153 #else
154  Packet4f inv, restep, div;
155 
156  // NEON does not offer a divide instruction, we have to do a reciprocal approximation
157  // However NEON in contrast to other SIMD engines (AltiVec/SSE), offers
158  // a reciprocal estimate AND a reciprocal step -which saves a few instructions
159  // vrecpeq_f32() returns an estimate to 1/b, which we will finetune with
160  // Newton-Raphson and vrecpsq_f32()
161  inv = vrecpeq_f32(b);
162 
163  // This returns a differential, by which we will have to multiply inv to get a better
164  // approximation of 1/b.
165  restep = vrecpsq_f32(b, inv);
166  inv = vmulq_f32(restep, inv);
167 
168  // Finally, multiply a by 1/b and get the wanted result of the division.
169  div = vmulq_f32(a, inv);
170 
171  return div;
172 #endif
173 }
174 
175 template<> EIGEN_STRONG_INLINE Packet4i pdiv<Packet4i>(const Packet4i& /*a*/, const Packet4i& /*b*/)
176 { eigen_assert(false && "packet integer division are not supported by NEON");
177  return pset1<Packet4i>(0);
178 }
179 
180 #ifdef __ARM_FEATURE_FMA
181 // See bug 936.
182 // FMA is available on VFPv4 i.e. when compiling with -mfpu=neon-vfpv4.
183 // FMA is a true fused multiply-add i.e. only 1 rounding at the end, no intermediate rounding.
184 // MLA is not fused i.e. does 2 roundings.
185 // In addition to giving better accuracy, FMA also gives better performance here on a Krait (Nexus 4):
186 // MLA: 10 GFlop/s ; FMA: 12 GFlops/s.
187 template<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c) { return vfmaq_f32(c,a,b); }
188 #else
189 template<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c) { return vmlaq_f32(c,a,b); }
190 #endif
191 
192 // No FMA instruction for int, so use MLA unconditionally.
193 template<> EIGEN_STRONG_INLINE Packet4i pmadd(const Packet4i& a, const Packet4i& b, const Packet4i& c) { return vmlaq_s32(c,a,b); }
194 
195 template<> EIGEN_STRONG_INLINE Packet4f pmin<Packet4f>(const Packet4f& a, const Packet4f& b) { return vminq_f32(a,b); }
196 template<> EIGEN_STRONG_INLINE Packet4i pmin<Packet4i>(const Packet4i& a, const Packet4i& b) { return vminq_s32(a,b); }
197 
198 template<> EIGEN_STRONG_INLINE Packet4f pmax<Packet4f>(const Packet4f& a, const Packet4f& b) { return vmaxq_f32(a,b); }
199 template<> EIGEN_STRONG_INLINE Packet4i pmax<Packet4i>(const Packet4i& a, const Packet4i& b) { return vmaxq_s32(a,b); }
200 
201 // Logical Operations are not supported for float, so we have to reinterpret casts using NEON intrinsics
202 template<> EIGEN_STRONG_INLINE Packet4f pand<Packet4f>(const Packet4f& a, const Packet4f& b)
203 {
204  return vreinterpretq_f32_u32(vandq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));
205 }
206 template<> EIGEN_STRONG_INLINE Packet4i pand<Packet4i>(const Packet4i& a, const Packet4i& b) { return vandq_s32(a,b); }
207 
208 template<> EIGEN_STRONG_INLINE Packet4f por<Packet4f>(const Packet4f& a, const Packet4f& b)
209 {
210  return vreinterpretq_f32_u32(vorrq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));
211 }
212 template<> EIGEN_STRONG_INLINE Packet4i por<Packet4i>(const Packet4i& a, const Packet4i& b) { return vorrq_s32(a,b); }
213 
214 template<> EIGEN_STRONG_INLINE Packet4f pxor<Packet4f>(const Packet4f& a, const Packet4f& b)
215 {
216  return vreinterpretq_f32_u32(veorq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));
217 }
218 template<> EIGEN_STRONG_INLINE Packet4i pxor<Packet4i>(const Packet4i& a, const Packet4i& b) { return veorq_s32(a,b); }
219 
220 template<> EIGEN_STRONG_INLINE Packet4f pandnot<Packet4f>(const Packet4f& a, const Packet4f& b)
221 {
222  return vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));
223 }
224 template<> EIGEN_STRONG_INLINE Packet4i pandnot<Packet4i>(const Packet4i& a, const Packet4i& b) { return vbicq_s32(a,b); }
225 
226 template<> EIGEN_STRONG_INLINE Packet4f pload<Packet4f>(const float* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_f32(from); }
227 template<> EIGEN_STRONG_INLINE Packet4i pload<Packet4i>(const int* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_s32(from); }
228 
229 template<> EIGEN_STRONG_INLINE Packet4f ploadu<Packet4f>(const float* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_f32(from); }
230 template<> EIGEN_STRONG_INLINE Packet4i ploadu<Packet4i>(const int* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_s32(from); }
231 
232 template<> EIGEN_STRONG_INLINE Packet4f ploaddup<Packet4f>(const float* from)
233 {
234  float32x2_t lo, hi;
235  lo = vld1_dup_f32(from);
236  hi = vld1_dup_f32(from+1);
237  return vcombine_f32(lo, hi);
238 }
239 template<> EIGEN_STRONG_INLINE Packet4i ploaddup<Packet4i>(const int* from)
240 {
241  int32x2_t lo, hi;
242  lo = vld1_dup_s32(from);
243  hi = vld1_dup_s32(from+1);
244  return vcombine_s32(lo, hi);
245 }
246 
247 template<> EIGEN_STRONG_INLINE void pstore<float>(float* to, const Packet4f& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_f32(to, from); }
248 template<> EIGEN_STRONG_INLINE void pstore<int>(int* to, const Packet4i& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_s32(to, from); }
249 
250 template<> EIGEN_STRONG_INLINE void pstoreu<float>(float* to, const Packet4f& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_f32(to, from); }
251 template<> EIGEN_STRONG_INLINE void pstoreu<int>(int* to, const Packet4i& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_s32(to, from); }
252 
253 template<> EIGEN_DEVICE_FUNC inline Packet4f pgather<float, Packet4f>(const float* from, Index stride)
254 {
255  Packet4f res = pset1<Packet4f>(0.f);
256  res = vsetq_lane_f32(from[0*stride], res, 0);
257  res = vsetq_lane_f32(from[1*stride], res, 1);
258  res = vsetq_lane_f32(from[2*stride], res, 2);
259  res = vsetq_lane_f32(from[3*stride], res, 3);
260  return res;
261 }
262 template<> EIGEN_DEVICE_FUNC inline Packet4i pgather<int, Packet4i>(const int* from, Index stride)
263 {
264  Packet4i res = pset1<Packet4i>(0);
265  res = vsetq_lane_s32(from[0*stride], res, 0);
266  res = vsetq_lane_s32(from[1*stride], res, 1);
267  res = vsetq_lane_s32(from[2*stride], res, 2);
268  res = vsetq_lane_s32(from[3*stride], res, 3);
269  return res;
270 }
271 
272 template<> EIGEN_DEVICE_FUNC inline void pscatter<float, Packet4f>(float* to, const Packet4f& from, Index stride)
273 {
274  to[stride*0] = vgetq_lane_f32(from, 0);
275  to[stride*1] = vgetq_lane_f32(from, 1);
276  to[stride*2] = vgetq_lane_f32(from, 2);
277  to[stride*3] = vgetq_lane_f32(from, 3);
278 }
279 template<> EIGEN_DEVICE_FUNC inline void pscatter<int, Packet4i>(int* to, const Packet4i& from, Index stride)
280 {
281  to[stride*0] = vgetq_lane_s32(from, 0);
282  to[stride*1] = vgetq_lane_s32(from, 1);
283  to[stride*2] = vgetq_lane_s32(from, 2);
284  to[stride*3] = vgetq_lane_s32(from, 3);
285 }
286 
287 template<> EIGEN_STRONG_INLINE void prefetch<float>(const float* addr) { EIGEN_ARM_PREFETCH(addr); }
288 template<> EIGEN_STRONG_INLINE void prefetch<int>(const int* addr) { EIGEN_ARM_PREFETCH(addr); }
289 
290 // FIXME only store the 2 first elements ?
291 template<> EIGEN_STRONG_INLINE float pfirst<Packet4f>(const Packet4f& a) { float EIGEN_ALIGN16 x[4]; vst1q_f32(x, a); return x[0]; }
292 template<> EIGEN_STRONG_INLINE int pfirst<Packet4i>(const Packet4i& a) { int EIGEN_ALIGN16 x[4]; vst1q_s32(x, a); return x[0]; }
293 
294 template<> EIGEN_STRONG_INLINE Packet4f preverse(const Packet4f& a) {
295  float32x2_t a_lo, a_hi;
296  Packet4f a_r64;
297 
298  a_r64 = vrev64q_f32(a);
299  a_lo = vget_low_f32(a_r64);
300  a_hi = vget_high_f32(a_r64);
301  return vcombine_f32(a_hi, a_lo);
302 }
303 template<> EIGEN_STRONG_INLINE Packet4i preverse(const Packet4i& a) {
304  int32x2_t a_lo, a_hi;
305  Packet4i a_r64;
306 
307  a_r64 = vrev64q_s32(a);
308  a_lo = vget_low_s32(a_r64);
309  a_hi = vget_high_s32(a_r64);
310  return vcombine_s32(a_hi, a_lo);
311 }
312 
313 template<size_t offset>
314 struct protate_impl<offset, Packet4f>
315 {
316  static Packet4f run(const Packet4f& a) {
317  return vextq_f32(a, a, offset);
318  }
319 };
320 
321 template<size_t offset>
322 struct protate_impl<offset, Packet4i>
323 {
324  static Packet4i run(const Packet4i& a) {
325  return vextq_s32(a, a, offset);
326  }
327 };
328 
329 template<> EIGEN_STRONG_INLINE Packet4f pabs(const Packet4f& a) { return vabsq_f32(a); }
330 template<> EIGEN_STRONG_INLINE Packet4i pabs(const Packet4i& a) { return vabsq_s32(a); }
331 
332 template<> EIGEN_STRONG_INLINE float predux<Packet4f>(const Packet4f& a)
333 {
334  float32x2_t a_lo, a_hi, sum;
335 
336  a_lo = vget_low_f32(a);
337  a_hi = vget_high_f32(a);
338  sum = vpadd_f32(a_lo, a_hi);
339  sum = vpadd_f32(sum, sum);
340  return vget_lane_f32(sum, 0);
341 }
342 
343 template<> EIGEN_STRONG_INLINE Packet4f preduxp<Packet4f>(const Packet4f* vecs)
344 {
345  float32x4x2_t vtrn1, vtrn2, res1, res2;
346  Packet4f sum1, sum2, sum;
347 
348  // NEON zip performs interleaving of the supplied vectors.
349  // We perform two interleaves in a row to acquire the transposed vector
350  vtrn1 = vzipq_f32(vecs[0], vecs[2]);
351  vtrn2 = vzipq_f32(vecs[1], vecs[3]);
352  res1 = vzipq_f32(vtrn1.val[0], vtrn2.val[0]);
353  res2 = vzipq_f32(vtrn1.val[1], vtrn2.val[1]);
354 
355  // Do the addition of the resulting vectors
356  sum1 = vaddq_f32(res1.val[0], res1.val[1]);
357  sum2 = vaddq_f32(res2.val[0], res2.val[1]);
358  sum = vaddq_f32(sum1, sum2);
359 
360  return sum;
361 }
362 
363 template<> EIGEN_STRONG_INLINE int predux<Packet4i>(const Packet4i& a)
364 {
365  int32x2_t a_lo, a_hi, sum;
366 
367  a_lo = vget_low_s32(a);
368  a_hi = vget_high_s32(a);
369  sum = vpadd_s32(a_lo, a_hi);
370  sum = vpadd_s32(sum, sum);
371  return vget_lane_s32(sum, 0);
372 }
373 
374 template<> EIGEN_STRONG_INLINE Packet4i preduxp<Packet4i>(const Packet4i* vecs)
375 {
376  int32x4x2_t vtrn1, vtrn2, res1, res2;
377  Packet4i sum1, sum2, sum;
378 
379  // NEON zip performs interleaving of the supplied vectors.
380  // We perform two interleaves in a row to acquire the transposed vector
381  vtrn1 = vzipq_s32(vecs[0], vecs[2]);
382  vtrn2 = vzipq_s32(vecs[1], vecs[3]);
383  res1 = vzipq_s32(vtrn1.val[0], vtrn2.val[0]);
384  res2 = vzipq_s32(vtrn1.val[1], vtrn2.val[1]);
385 
386  // Do the addition of the resulting vectors
387  sum1 = vaddq_s32(res1.val[0], res1.val[1]);
388  sum2 = vaddq_s32(res2.val[0], res2.val[1]);
389  sum = vaddq_s32(sum1, sum2);
390 
391  return sum;
392 }
393 
394 // Other reduction functions:
395 // mul
396 template<> EIGEN_STRONG_INLINE float predux_mul<Packet4f>(const Packet4f& a)
397 {
398  float32x2_t a_lo, a_hi, prod;
399 
400  // Get a_lo = |a1|a2| and a_hi = |a3|a4|
401  a_lo = vget_low_f32(a);
402  a_hi = vget_high_f32(a);
403  // Get the product of a_lo * a_hi -> |a1*a3|a2*a4|
404  prod = vmul_f32(a_lo, a_hi);
405  // Multiply prod with its swapped value |a2*a4|a1*a3|
406  prod = vmul_f32(prod, vrev64_f32(prod));
407 
408  return vget_lane_f32(prod, 0);
409 }
410 template<> EIGEN_STRONG_INLINE int predux_mul<Packet4i>(const Packet4i& a)
411 {
412  int32x2_t a_lo, a_hi, prod;
413 
414  // Get a_lo = |a1|a2| and a_hi = |a3|a4|
415  a_lo = vget_low_s32(a);
416  a_hi = vget_high_s32(a);
417  // Get the product of a_lo * a_hi -> |a1*a3|a2*a4|
418  prod = vmul_s32(a_lo, a_hi);
419  // Multiply prod with its swapped value |a2*a4|a1*a3|
420  prod = vmul_s32(prod, vrev64_s32(prod));
421 
422  return vget_lane_s32(prod, 0);
423 }
424 
425 // min
426 template<> EIGEN_STRONG_INLINE float predux_min<Packet4f>(const Packet4f& a)
427 {
428  float32x2_t a_lo, a_hi, min;
429 
430  a_lo = vget_low_f32(a);
431  a_hi = vget_high_f32(a);
432  min = vpmin_f32(a_lo, a_hi);
433  min = vpmin_f32(min, min);
434 
435  return vget_lane_f32(min, 0);
436 }
437 
438 template<> EIGEN_STRONG_INLINE int predux_min<Packet4i>(const Packet4i& a)
439 {
440  int32x2_t a_lo, a_hi, min;
441 
442  a_lo = vget_low_s32(a);
443  a_hi = vget_high_s32(a);
444  min = vpmin_s32(a_lo, a_hi);
445  min = vpmin_s32(min, min);
446 
447  return vget_lane_s32(min, 0);
448 }
449 
450 // max
451 template<> EIGEN_STRONG_INLINE float predux_max<Packet4f>(const Packet4f& a)
452 {
453  float32x2_t a_lo, a_hi, max;
454 
455  a_lo = vget_low_f32(a);
456  a_hi = vget_high_f32(a);
457  max = vpmax_f32(a_lo, a_hi);
458  max = vpmax_f32(max, max);
459 
460  return vget_lane_f32(max, 0);
461 }
462 
463 template<> EIGEN_STRONG_INLINE int predux_max<Packet4i>(const Packet4i& a)
464 {
465  int32x2_t a_lo, a_hi, max;
466 
467  a_lo = vget_low_s32(a);
468  a_hi = vget_high_s32(a);
469  max = vpmax_s32(a_lo, a_hi);
470  max = vpmax_s32(max, max);
471 
472  return vget_lane_s32(max, 0);
473 }
474 
475 // this PALIGN_NEON business is to work around a bug in LLVM Clang 3.0 causing incorrect compilation errors,
476 // see bug 347 and this LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=11074
477 #define PALIGN_NEON(Offset,Type,Command) \
478 template<>\
479 struct palign_impl<Offset,Type>\
480 {\
481  EIGEN_STRONG_INLINE static void run(Type& first, const Type& second)\
482  {\
483  if (Offset!=0)\
484  first = Command(first, second, Offset);\
485  }\
486 };\
487 
488 PALIGN_NEON(0,Packet4f,vextq_f32)
489 PALIGN_NEON(1,Packet4f,vextq_f32)
490 PALIGN_NEON(2,Packet4f,vextq_f32)
491 PALIGN_NEON(3,Packet4f,vextq_f32)
492 PALIGN_NEON(0,Packet4i,vextq_s32)
493 PALIGN_NEON(1,Packet4i,vextq_s32)
494 PALIGN_NEON(2,Packet4i,vextq_s32)
495 PALIGN_NEON(3,Packet4i,vextq_s32)
496 
497 #undef PALIGN_NEON
498 
499 EIGEN_DEVICE_FUNC inline void
500 ptranspose(PacketBlock<Packet4f,4>& kernel) {
501  float32x4x2_t tmp1 = vzipq_f32(kernel.packet[0], kernel.packet[1]);
502  float32x4x2_t tmp2 = vzipq_f32(kernel.packet[2], kernel.packet[3]);
503 
504  kernel.packet[0] = vcombine_f32(vget_low_f32(tmp1.val[0]), vget_low_f32(tmp2.val[0]));
505  kernel.packet[1] = vcombine_f32(vget_high_f32(tmp1.val[0]), vget_high_f32(tmp2.val[0]));
506  kernel.packet[2] = vcombine_f32(vget_low_f32(tmp1.val[1]), vget_low_f32(tmp2.val[1]));
507  kernel.packet[3] = vcombine_f32(vget_high_f32(tmp1.val[1]), vget_high_f32(tmp2.val[1]));
508 }
509 
510 EIGEN_DEVICE_FUNC inline void
511 ptranspose(PacketBlock<Packet4i,4>& kernel) {
512  int32x4x2_t tmp1 = vzipq_s32(kernel.packet[0], kernel.packet[1]);
513  int32x4x2_t tmp2 = vzipq_s32(kernel.packet[2], kernel.packet[3]);
514  kernel.packet[0] = vcombine_s32(vget_low_s32(tmp1.val[0]), vget_low_s32(tmp2.val[0]));
515  kernel.packet[1] = vcombine_s32(vget_high_s32(tmp1.val[0]), vget_high_s32(tmp2.val[0]));
516  kernel.packet[2] = vcombine_s32(vget_low_s32(tmp1.val[1]), vget_low_s32(tmp2.val[1]));
517  kernel.packet[3] = vcombine_s32(vget_high_s32(tmp1.val[1]), vget_high_s32(tmp2.val[1]));
518 }
519 
520 //---------- double ----------
521 
522 // Clang 3.5 in the iOS toolchain has an ICE triggered by NEON intrisics for double.
523 // Confirmed at least with __apple_build_version__ = 6000054.
524 #ifdef __apple_build_version__
525 // Let's hope that by the time __apple_build_version__ hits the 601* range, the bug will be fixed.
526 // https://gist.github.com/yamaya/2924292 suggests that the 3 first digits are only updated with
527 // major toolchain updates.
528 #define EIGEN_APPLE_DOUBLE_NEON_BUG (__apple_build_version__ < 6010000)
529 #else
530 #define EIGEN_APPLE_DOUBLE_NEON_BUG 0
531 #endif
532 
533 #if EIGEN_ARCH_ARM64 && !EIGEN_APPLE_DOUBLE_NEON_BUG
534 
535 #if (EIGEN_COMP_GNUC_STRICT && defined(__ANDROID__)) || defined(__apple_build_version__)
536 // Bug 907: workaround missing declarations of the following two functions in the ADK
537 __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
538 vreinterpretq_u64_f64 (float64x2_t __a)
539 {
540  return (uint64x2_t) __a;
541 }
542 
543 __extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
544 vreinterpretq_f64_u64 (uint64x2_t __a)
545 {
546  return (float64x2_t) __a;
547 }
548 #endif
549 
550 typedef float64x2_t Packet2d;
551 typedef float64x1_t Packet1d;
552 
553 template<> struct packet_traits<double> : default_packet_traits
554 {
555  typedef Packet2d type;
556  typedef Packet2d half;
557  enum {
558  Vectorizable = 1,
559  AlignedOnScalar = 1,
560  size = 2,
561  HasHalfPacket=0,
562 
563  HasDiv = 1,
564  // FIXME check the Has*
565  HasSin = 0,
566  HasCos = 0,
567  HasLog = 0,
568  HasExp = 0,
569  HasSqrt = 0
570  };
571 };
572 
573 template<> struct unpacket_traits<Packet2d> { typedef double type; enum {size=2, alignment=Aligned16}; typedef Packet2d half; };
574 
575 template<> EIGEN_STRONG_INLINE Packet2d pset1<Packet2d>(const double& from) { return vdupq_n_f64(from); }
576 
577 template<> EIGEN_STRONG_INLINE Packet2d plset<Packet2d>(const double& a)
578 {
579  Packet2d countdown = EIGEN_INIT_NEON_PACKET2(0, 1);
580  return vaddq_f64(pset1<Packet2d>(a), countdown);
581 }
582 template<> EIGEN_STRONG_INLINE Packet2d padd<Packet2d>(const Packet2d& a, const Packet2d& b) { return vaddq_f64(a,b); }
583 
584 template<> EIGEN_STRONG_INLINE Packet2d psub<Packet2d>(const Packet2d& a, const Packet2d& b) { return vsubq_f64(a,b); }
585 
586 template<> EIGEN_STRONG_INLINE Packet2d pnegate(const Packet2d& a) { return vnegq_f64(a); }
587 
588 template<> EIGEN_STRONG_INLINE Packet2d pconj(const Packet2d& a) { return a; }
589 
590 template<> EIGEN_STRONG_INLINE Packet2d pmul<Packet2d>(const Packet2d& a, const Packet2d& b) { return vmulq_f64(a,b); }
591 
592 template<> EIGEN_STRONG_INLINE Packet2d pdiv<Packet2d>(const Packet2d& a, const Packet2d& b) { return vdivq_f64(a,b); }
593 
594 #ifdef __ARM_FEATURE_FMA
595 // See bug 936. See above comment about FMA for float.
596 template<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return vfmaq_f64(c,a,b); }
597 #else
598 template<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return vmlaq_f64(c,a,b); }
599 #endif
600 
601 template<> EIGEN_STRONG_INLINE Packet2d pmin<Packet2d>(const Packet2d& a, const Packet2d& b) { return vminq_f64(a,b); }
602 
603 template<> EIGEN_STRONG_INLINE Packet2d pmax<Packet2d>(const Packet2d& a, const Packet2d& b) { return vmaxq_f64(a,b); }
604 
605 // Logical Operations are not supported for float, so we have to reinterpret casts using NEON intrinsics
606 template<> EIGEN_STRONG_INLINE Packet2d pand<Packet2d>(const Packet2d& a, const Packet2d& b)
607 {
608  return vreinterpretq_f64_u64(vandq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));
609 }
610 
611 template<> EIGEN_STRONG_INLINE Packet2d por<Packet2d>(const Packet2d& a, const Packet2d& b)
612 {
613  return vreinterpretq_f64_u64(vorrq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));
614 }
615 
616 template<> EIGEN_STRONG_INLINE Packet2d pxor<Packet2d>(const Packet2d& a, const Packet2d& b)
617 {
618  return vreinterpretq_f64_u64(veorq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));
619 }
620 
621 template<> EIGEN_STRONG_INLINE Packet2d pandnot<Packet2d>(const Packet2d& a, const Packet2d& b)
622 {
623  return vreinterpretq_f64_u64(vbicq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));
624 }
625 
626 template<> EIGEN_STRONG_INLINE Packet2d pload<Packet2d>(const double* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_f64(from); }
627 
628 template<> EIGEN_STRONG_INLINE Packet2d ploadu<Packet2d>(const double* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_f64(from); }
629 
630 template<> EIGEN_STRONG_INLINE Packet2d ploaddup<Packet2d>(const double* from)
631 {
632  return vld1q_dup_f64(from);
633 }
634 template<> EIGEN_STRONG_INLINE void pstore<double>(double* to, const Packet2d& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_f64(to, from); }
635 
636 template<> EIGEN_STRONG_INLINE void pstoreu<double>(double* to, const Packet2d& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_f64(to, from); }
637 
638 template<> EIGEN_DEVICE_FUNC inline Packet2d pgather<double, Packet2d>(const double* from, Index stride)
639 {
640  Packet2d res = pset1<Packet2d>(0.0);
641  res = vsetq_lane_f64(from[0*stride], res, 0);
642  res = vsetq_lane_f64(from[1*stride], res, 1);
643  return res;
644 }
645 template<> EIGEN_DEVICE_FUNC inline void pscatter<double, Packet2d>(double* to, const Packet2d& from, Index stride)
646 {
647  to[stride*0] = vgetq_lane_f64(from, 0);
648  to[stride*1] = vgetq_lane_f64(from, 1);
649 }
650 template<> EIGEN_STRONG_INLINE void prefetch<double>(const double* addr) { EIGEN_ARM_PREFETCH(addr); }
651 
652 // FIXME only store the 2 first elements ?
653 template<> EIGEN_STRONG_INLINE double pfirst<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(a, 0); }
654 
655 template<> EIGEN_STRONG_INLINE Packet2d preverse(const Packet2d& a) { return vcombine_f64(vget_high_f64(a), vget_low_f64(a)); }
656 
657 template<size_t offset>
658 struct protate_impl<offset, Packet2d>
659 {
660  static Packet2d run(const Packet2d& a) {
661  return vextq_f64(a, a, offset);
662  }
663 };
664 
665 template<> EIGEN_STRONG_INLINE Packet2d pabs(const Packet2d& a) { return vabsq_f64(a); }
666 
667 #if EIGEN_COMP_CLANG && defined(__apple_build_version__)
668 // workaround ICE, see bug 907
669 template<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a) { return (vget_low_f64(a) + vget_high_f64(a))[0]; }
670 #else
671 template<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a) { return vget_lane_f64(vget_low_f64(a) + vget_high_f64(a), 0); }
672 #endif
673 
674 template<> EIGEN_STRONG_INLINE Packet2d preduxp<Packet2d>(const Packet2d* vecs)
675 {
676  float64x2_t trn1, trn2;
677 
678  // NEON zip performs interleaving of the supplied vectors.
679  // We perform two interleaves in a row to acquire the transposed vector
680  trn1 = vzip1q_f64(vecs[0], vecs[1]);
681  trn2 = vzip2q_f64(vecs[0], vecs[1]);
682 
683  // Do the addition of the resulting vectors
684  return vaddq_f64(trn1, trn2);
685 }
686 // Other reduction functions:
687 // mul
688 #if EIGEN_COMP_CLANG && defined(__apple_build_version__)
689 template<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a) { return (vget_low_f64(a) * vget_high_f64(a))[0]; }
690 #else
691 template<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a) { return vget_lane_f64(vget_low_f64(a) * vget_high_f64(a), 0); }
692 #endif
693 
694 // min
695 template<> EIGEN_STRONG_INLINE double predux_min<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(vpminq_f64(a, a), 0); }
696 
697 // max
698 template<> EIGEN_STRONG_INLINE double predux_max<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(vpmaxq_f64(a, a), 0); }
699 
700 // this PALIGN_NEON business is to work around a bug in LLVM Clang 3.0 causing incorrect compilation errors,
701 // see bug 347 and this LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=11074
702 #define PALIGN_NEON(Offset,Type,Command) \
703 template<>\
704 struct palign_impl<Offset,Type>\
705 {\
706  EIGEN_STRONG_INLINE static void run(Type& first, const Type& second)\
707  {\
708  if (Offset!=0)\
709  first = Command(first, second, Offset);\
710  }\
711 };\
712 
713 PALIGN_NEON(0,Packet2d,vextq_f64)
714 PALIGN_NEON(1,Packet2d,vextq_f64)
715 #undef PALIGN_NEON
716 
717 EIGEN_DEVICE_FUNC inline void
718 ptranspose(PacketBlock<Packet2d,2>& kernel) {
719  float64x2_t trn1 = vzip1q_f64(kernel.packet[0], kernel.packet[1]);
720  float64x2_t trn2 = vzip2q_f64(kernel.packet[0], kernel.packet[1]);
721 
722  kernel.packet[0] = trn1;
723  kernel.packet[1] = trn2;
724 }
725 #endif // EIGEN_ARCH_ARM64
726 
727 } // end namespace internal
728 
729 } // end namespace Eigen
730 
731 #endif // EIGEN_PACKET_MATH_NEON_H
Definition: LDLT.h:16
Definition: Constants.h:222
Definition: Eigen_Colamd.h:54