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include
avr
sleep.h
Go to the documentation of this file.
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/* Copyright (c) 2002, 2004 Theodore A. Roth
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Copyright (c) 2004, 2007, 2008 Eric B. Weddington
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Copyright (c) 2005, 2006, 2007 Joerg Wunsch
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id$ */
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#ifndef _AVR_SLEEP_H_
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#define _AVR_SLEEP_H_ 1
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#include <
avr/io.h
>
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#include <
stdint.h
>
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/** \file */
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/** \defgroup avr_sleep <avr/sleep.h>: Power Management and Sleep Modes
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\code #include <avr/sleep.h>\endcode
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Use of the \c SLEEP instruction can allow an application to reduce its
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power comsumption considerably. AVR devices can be put into different
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sleep modes. Refer to the datasheet for the details relating to the device
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you are using.
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There are several macros provided in this header file to actually
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put the device into sleep mode. The simplest way is to optionally
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set the desired sleep mode using \c set_sleep_mode() (it usually
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defaults to idle mode where the CPU is put on sleep but all
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peripheral clocks are still running), and then call
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\c sleep_mode(). This macro automatically sets the sleep enable bit, goes
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to sleep, and clears the sleep enable bit.
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Example:
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\code
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#include <avr/sleep.h>
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...
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set_sleep_mode(<mode>);
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sleep_mode();
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\endcode
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Note that unless your purpose is to completely lock the CPU (until a
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hardware reset), interrupts need to be enabled before going to sleep.
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As the \c sleep_mode() macro might cause race conditions in some
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situations, the individual steps of manipulating the sleep enable
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(SE) bit, and actually issuing the \c SLEEP instruction, are provided
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in the macros \c sleep_enable(), \c sleep_disable(), and
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\c sleep_cpu(). This also allows for test-and-sleep scenarios that
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take care of not missing the interrupt that will awake the device
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from sleep.
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Example:
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\code
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#include <avr/interrupt.h>
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#include <avr/sleep.h>
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...
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set_sleep_mode(<mode>);
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cli();
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if (some_condition)
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{
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sleep_enable();
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sei();
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sleep_cpu();
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sleep_disable();
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}
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sei();
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\endcode
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This sequence ensures an atomic test of \c some_condition with
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interrupts being disabled. If the condition is met, sleep mode
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will be prepared, and the \c SLEEP instruction will be scheduled
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immediately after an \c SEI instruction. As the intruction right
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after the \c SEI is guaranteed to be executed before an interrupt
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could trigger, it is sure the device will really be put to sleep.
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Some devices have the ability to disable the Brown Out Detector (BOD) before
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going to sleep. This will also reduce power while sleeping. If the
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specific AVR device has this ability then an additional macro is defined:
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\c sleep_bod_disable(). This macro generates inlined assembly code
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that will correctly implement the timed sequence for disabling the BOD
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before sleeping. However, there is a limited number of cycles after the
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BOD has been disabled that the device can be put into sleep mode, otherwise
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the BOD will not truly be disabled. Recommended practice is to disable
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the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then
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put the device to sleep (\c sleep_cpu()), like so:
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\code
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#include <avr/interrupt.h>
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#include <avr/sleep.h>
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...
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set_sleep_mode(<mode>);
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cli();
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if (some_condition)
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{
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sleep_enable();
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sleep_bod_disable();
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sei();
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sleep_cpu();
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sleep_disable();
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}
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sei();
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\endcode
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*/
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/* Define an internal sleep control register and an internal sleep enable bit mask. */
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#if defined(SLEEP_CTRL)
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/* XMEGA devices */
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#define _SLEEP_CONTROL_REG SLEEP_CTRL
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#define _SLEEP_ENABLE_MASK SLEEP_SEN_bm
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#elif defined(SMCR)
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#define _SLEEP_CONTROL_REG SMCR
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#define _SLEEP_ENABLE_MASK _BV(SE)
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#elif defined(__AVR_AT94K__)
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#define _SLEEP_CONTROL_REG MCUR
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#define _SLEEP_ENABLE_MASK _BV(SE)
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#else
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#define _SLEEP_CONTROL_REG MCUCR
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#define _SLEEP_ENABLE_MASK _BV(SE)
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#endif
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/* Define set_sleep_mode() and sleep mode values per device. */
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#if defined(__AVR_ATmega161__)
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#define SLEEP_MODE_IDLE 0
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#define SLEEP_MODE_PWR_DOWN 1
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#define SLEEP_MODE_PWR_SAVE 2
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#define set_sleep_mode(mode) \
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do { \
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MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
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EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
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} while(0)
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#elif defined(__AVR_ATmega162__) \
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|| defined(__AVR_ATmega8515__)
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#define SLEEP_MODE_IDLE 0
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#define SLEEP_MODE_PWR_DOWN 1
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#define SLEEP_MODE_PWR_SAVE 2
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#define SLEEP_MODE_ADC 3
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#define SLEEP_MODE_STANDBY 4
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#define SLEEP_MODE_EXT_STANDBY 5
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#define set_sleep_mode(mode) \
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do { \
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MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
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MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
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EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
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} while(0)
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#elif defined(__AVR_AT90S2313__) \
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|| defined(__AVR_AT90S2323__) \
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|| defined(__AVR_AT90S2333__) \
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|| defined(__AVR_AT90S2343__) \
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|| defined(__AVR_AT43USB320__) \
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|| defined(__AVR_AT43USB355__) \
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|| defined(__AVR_AT90S4414__) \
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|| defined(__AVR_AT90S4433__) \
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|| defined(__AVR_AT90S8515__) \
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|| defined(__AVR_ATtiny22__)
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#define SLEEP_MODE_IDLE 0
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#define SLEEP_MODE_PWR_DOWN _BV(SM)
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#define set_sleep_mode(mode) \
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do { \
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_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~_BV(SM)) | (mode)); \
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} while(0)
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#elif defined(__AVR_ATA6616C__) \
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|| defined(__AVR_ATA6617C__) \
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|| defined(__AVR_ATA664251__) \
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|| defined(__AVR_ATtiny167__) \
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|| defined(__AVR_ATtiny87__) \
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|| defined(__AVR_ATtiny441__) \
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|| defined(__AVR_ATtiny828__) \
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|| defined(__AVR_ATtiny841__)
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#define SLEEP_MODE_IDLE 0
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#define SLEEP_MODE_ADC _BV(SM0)
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#define SLEEP_MODE_PWR_DOWN _BV(SM1)
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#define set_sleep_mode(mode) \
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do { \
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_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
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} while(0)
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#elif defined(__AVR_AT90S4434__) \
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|| defined(__AVR_ATA5505__) \
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|| defined(__AVR_ATA5272__) \
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|| defined(__AVR_AT76C711__) \
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|| defined(__AVR_AT90S8535__) \
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|| defined(__AVR_ATmega103__) \
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|| defined(__AVR_ATmega161__) \
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|| defined(__AVR_ATmega163__) \
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|| defined(__AVR_ATmega16HVB__) \
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|| defined(__AVR_ATmega16HVBREVB__) \
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|| defined(__AVR_ATmega32HVB__) \
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|| defined(__AVR_ATmega32HVBREVB__) \
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|| defined(__AVR_ATtiny13__) \
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|| defined(__AVR_ATtiny13A__) \
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|| defined(__AVR_ATtiny15__) \
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|| defined(__AVR_ATtiny24__) \
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|| defined(__AVR_ATtiny24A__) \
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|| defined(__AVR_ATtiny44__) \
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|| defined(__AVR_ATtiny44A__) \
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|| defined(__AVR_ATtiny84__) \
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|| defined(__AVR_ATtiny84A__) \
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|| defined(__AVR_ATtiny25__) \
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|| defined(__AVR_ATtiny45__) \
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|| defined(__AVR_ATtiny48__) \
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|| defined(__AVR_ATtiny85__) \
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|| defined(__AVR_ATtiny88__)
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#define SLEEP_MODE_IDLE 0
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#define SLEEP_MODE_ADC _BV(SM0)
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#define SLEEP_MODE_PWR_DOWN _BV(SM1)
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#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
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#define set_sleep_mode(mode) \
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do { \
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_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
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} while(0)
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#elif defined(__AVR_ATmega16HVA__) \
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|| defined(__AVR_ATmega8HVA__)
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#define SLEEP_MODE_IDLE (0)
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#define SLEEP_MODE_ADC _BV(SM0)
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#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
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#define SLEEP_MODE_PWR_OFF _BV(SM2)
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#define set_sleep_mode(mode) \
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do { \
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_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
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} while(0)
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#elif defined(__AVR_ATmega406__)
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#define SLEEP_MODE_IDLE (0)
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#define SLEEP_MODE_ADC _BV(SM0)
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#define SLEEP_MODE_PWR_DOWN _BV(SM1)
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#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
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#define SLEEP_MODE_PWR_OFF _BV(SM2)
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#define set_sleep_mode(mode) \
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do { \
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_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
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} while(0)
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#elif defined(__AVR_ATtiny2313__) \
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|| defined(__AVR_ATtiny2313A__) \
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|| defined(__AVR_ATtiny4313__)
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#define SLEEP_MODE_IDLE 0
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#define SLEEP_MODE_PWR_DOWN (_BV(SM0) | _BV(SM1))
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#define SLEEP_MODE_STANDBY _BV(SM1)
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#define set_sleep_mode(mode) \
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do { \
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_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
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} while(0)
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#elif defined(__AVR_AT94K__) \
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|| defined(__AVR_ATmega64HVE__) \
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|| defined(__AVR_ATmega64HVE2__)
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#define SLEEP_MODE_IDLE 0
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#define SLEEP_MODE_PWR_DOWN _BV(SM1)
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#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
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315
#define set_sleep_mode(mode) \
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do { \
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_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
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} while(0)
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#elif defined(__AVR_ATtiny26__) \
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|| defined(__AVR_ATtiny261__) \
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|| defined(__AVR_ATtiny261A__) \
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|| defined(__AVR_ATtiny461__) \
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|| defined(__AVR_ATtiny461A__) \
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|| defined(__AVR_ATtiny861__) \
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|| defined(__AVR_ATtiny861A__) \
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|| defined(__AVR_ATtiny43U__) \
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|| defined(__AVR_ATtiny1634__)
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#define SLEEP_MODE_IDLE 0
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#define SLEEP_MODE_ADC _BV(SM0)
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#define SLEEP_MODE_PWR_DOWN _BV(SM1)
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#define SLEEP_MODE_STANDBY (_BV(SM0) | _BV(SM1))
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#define set_sleep_mode(mode) \
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do { \
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_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
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} while(0)
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#elif defined(__AVR_AT90PWM216__) \
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|| defined(__AVR_AT90PWM316__) \
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|| defined(__AVR_AT90PWM161__) \
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|| defined(__AVR_AT90PWM81__) \
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|| defined(__AVR_AT90PWM1__) \
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|| defined(__AVR_AT90PWM2__) \
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|| defined(__AVR_AT90PWM2B__) \
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|| defined(__AVR_AT90PWM3__) \
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|| defined(__AVR_AT90PWM3B__) \
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|| defined(__AVR_ATmega32M1__) \
350
|| defined(__AVR_ATmega16M1__) \
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|| defined(__AVR_ATmega64M1__)
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#define SLEEP_MODE_IDLE 0
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#define SLEEP_MODE_ADC _BV(SM0)
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#define SLEEP_MODE_PWR_DOWN _BV(SM1)
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#define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
357
358
#define set_sleep_mode(mode) \
359
do { \
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_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
361
} while(0)
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363
#elif defined(__AVR_AT90USB1286__) \
364
|| defined(__AVR_AT90USB1287__) \
365
|| defined(__AVR_AT90USB646__) \
366
|| defined(__AVR_AT90USB647__) \
367
|| defined(__AVR_ATA6614Q__) \
368
|| defined(__AVR_ATmega128__) \
369
|| defined(__AVR_ATmega128A__) \
370
|| defined(__AVR_ATmega1280__) \
371
|| defined(__AVR_ATmega1281__) \
372
|| defined(__AVR_ATmega1284__) \
373
|| defined(__AVR_ATmega1284P__) \
374
|| defined(__AVR_ATmega128RFA1__) \
375
|| defined(__AVR_ATmega128RFR2__) \
376
|| defined(__AVR_ATmega1284RFR2__) \
377
|| defined(__AVR_ATmega16__) \
378
|| defined(__AVR_ATmega16A__) \
379
|| defined(__AVR_ATmega162__) \
380
|| defined(__AVR_ATmega164A__) \
381
|| defined(__AVR_ATmega164P__) \
382
|| defined(__AVR_ATmega164PA__) \
383
|| defined(__AVR_ATmega168A__) \
384
|| defined(__AVR_ATmega168P__) \
385
|| defined(__AVR_ATmega168PA__) \
386
|| defined(__AVR_ATmega168PB__) \
387
|| defined(__AVR_ATmega16HVA2__) \
388
|| defined(__AVR_ATmega16U4__) \
389
|| defined(__AVR_ATmega2560__) \
390
|| defined(__AVR_ATmega2561__) \
391
|| defined(__AVR_ATmega256RFR2__) \
392
|| defined(__AVR_ATmega2564RFR2__) \
393
|| defined(__AVR_ATmega32__) \
394
|| defined(__AVR_ATmega32A__) \
395
|| defined(__AVR_ATmega323__) \
396
|| defined(__AVR_ATmega324A__) \
397
|| defined(__AVR_ATmega324P__) \
398
|| defined(__AVR_ATmega324PA__) \
399
|| defined(__AVR_ATmega328__) \
400
|| defined(__AVR_ATmega328P__) \
401
|| defined(__AVR_ATmega32C1__) \
402
|| defined(__AVR_ATmega32U4__) \
403
|| defined(__AVR_ATmega32U6__) \
404
|| defined(__AVR_ATmega48A__) \
405
|| defined(__AVR_ATmega48PA__) \
406
|| defined(__AVR_ATmega48PB__) \
407
|| defined(__AVR_ATmega48P__) \
408
|| defined(__AVR_ATmega64__) \
409
|| defined(__AVR_ATmega64A__) \
410
|| defined(__AVR_ATmega640__) \
411
|| defined(__AVR_ATmega644__) \
412
|| defined(__AVR_ATmega644A__) \
413
|| defined(__AVR_ATmega644P__) \
414
|| defined(__AVR_ATmega644PA__) \
415
|| defined(__AVR_ATmega64C1__) \
416
|| defined(__AVR_ATmega64RFR2__) \
417
|| defined(__AVR_ATmega644RFR2__) \
418
|| defined(__AVR_ATmega8515__) \
419
|| defined(__AVR_ATmega8535__) \
420
|| defined(__AVR_ATmega88A__) \
421
|| defined(__AVR_ATmega88P__) \
422
|| defined(__AVR_ATmega88PA__) \
423
|| defined(__AVR_ATmega88PB__)
424
425
#define SLEEP_MODE_IDLE (0)
426
#define SLEEP_MODE_ADC _BV(SM0)
427
#define SLEEP_MODE_PWR_DOWN _BV(SM1)
428
#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
429
#define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
430
#define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
431
432
433
#define set_sleep_mode(mode) \
434
do { \
435
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
436
} while(0)
437
438
#elif defined(__AVR_ATmega8A__) \
439
|| defined(__AVR_ATmega8__) \
440
|| defined(__AVR_ATmega6450A__) \
441
|| defined(__AVR_ATmega6450P__) \
442
|| defined(__AVR_ATmega645A__) \
443
|| defined(__AVR_ATmega645P__) \
444
|| defined(__AVR_ATmega3250A__) \
445
|| defined(__AVR_ATmega3250PA__) \
446
|| defined(__AVR_ATmega325A__) \
447
|| defined(__AVR_ATmega325PA__) \
448
|| defined(__AVR_ATmega165A__) \
449
|| defined(__AVR_ATmega165P__) \
450
|| defined(__AVR_ATmega165PA__) \
451
|| defined(__AVR_ATmega169A__) \
452
|| defined(__AVR_ATmega169P__) \
453
|| defined(__AVR_ATmega169PA__) \
454
|| defined(__AVR_ATmega329A__) \
455
|| defined(__AVR_ATmega329PA__) \
456
|| defined(__AVR_ATmega3290A__) \
457
|| defined(__AVR_ATmega3290PA__) \
458
|| defined(__AVR_ATmega649A__) \
459
|| defined(__AVR_ATmega649P__) \
460
|| defined(__AVR_ATmega6490A__) \
461
|| defined(__AVR_ATmega6490P__) \
462
|| defined(__AVR_ATmega165__) \
463
|| defined(__AVR_ATmega169__) \
464
|| defined(__AVR_ATmega48__) \
465
|| defined(__AVR_ATmega88__) \
466
|| defined(__AVR_ATmega168__) \
467
|| defined(__AVR_ATmega325P__) \
468
|| defined(__AVR_ATmega3250P__) \
469
|| defined(__AVR_ATmega325__) \
470
|| defined(__AVR_ATmega3250__) \
471
|| defined(__AVR_ATmega645__) \
472
|| defined(__AVR_ATmega6450__) \
473
|| defined(__AVR_ATmega329__) \
474
|| defined(__AVR_ATmega329P__) \
475
|| defined(__AVR_ATmega3290__) \
476
|| defined(__AVR_ATmega3290P__) \
477
|| defined(__AVR_ATmega649__) \
478
|| defined(__AVR_ATmega6490__) \
479
|| defined(__AVR_AT90CAN128__) \
480
|| defined(__AVR_AT90CAN32__) \
481
|| defined(__AVR_AT90CAN64__) \
482
|| defined(__AVR_ATA6612C__) \
483
|| defined(__AVR_ATA6613C__)
484
485
#define SLEEP_MODE_IDLE (0)
486
#define SLEEP_MODE_ADC _BV(SM0)
487
#define SLEEP_MODE_PWR_DOWN _BV(SM1)
488
#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
489
#define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
490
491
492
#define set_sleep_mode(mode) \
493
do { \
494
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
495
} while(0)
496
497
#elif defined(__AVR_ATxmega16A4__) \
498
|| defined(__AVR_ATxmega16A4U__) \
499
|| defined(__AVR_ATxmega16C4__) \
500
|| defined(__AVR_ATxmega16D4__) \
501
|| defined(__AVR_ATxmega32A4__) \
502
|| defined(__AVR_ATxmega32A4U__) \
503
|| defined(__AVR_ATxmega32C3__) \
504
|| defined(__AVR_ATxmega32C4__) \
505
|| defined(__AVR_ATxmega32D3__) \
506
|| defined(__AVR_ATxmega32D4__) \
507
|| defined(__AVR_ATxmega8E5__) \
508
|| defined(__AVR_ATxmega16E5__) \
509
|| defined(__AVR_ATxmega32E5__) \
510
|| defined(__AVR_ATxmega64A1__) \
511
|| defined(__AVR_ATxmega64A1U__) \
512
|| defined(__AVR_ATxmega64A3__) \
513
|| defined(__AVR_ATxmega64A3U__) \
514
|| defined(__AVR_ATxmega64A4U__) \
515
|| defined(__AVR_ATxmega64B1__) \
516
|| defined(__AVR_ATxmega64B3__) \
517
|| defined(__AVR_ATxmega64C3__) \
518
|| defined(__AVR_ATxmega64D3__) \
519
|| defined(__AVR_ATxmega64D4__) \
520
|| defined(__AVR_ATxmega128A1__) \
521
|| defined(__AVR_ATxmega128A1U__) \
522
|| defined(__AVR_ATxmega128A3__) \
523
|| defined(__AVR_ATxmega128A3U__) \
524
|| defined(__AVR_ATxmega128A4U__) \
525
|| defined(__AVR_ATxmega128B1__) \
526
|| defined(__AVR_ATxmega128B3__) \
527
|| defined(__AVR_ATxmega128C3__) \
528
|| defined(__AVR_ATxmega128D3__) \
529
|| defined(__AVR_ATxmega128D4__) \
530
|| defined(__AVR_ATxmega192A3__) \
531
|| defined(__AVR_ATxmega192A3U__) \
532
|| defined(__AVR_ATxmega192C3__) \
533
|| defined(__AVR_ATxmega192D3__) \
534
|| defined(__AVR_ATxmega256A3__) \
535
|| defined(__AVR_ATxmega256A3U__) \
536
|| defined(__AVR_ATxmega256C3__) \
537
|| defined(__AVR_ATxmega256D3__) \
538
|| defined(__AVR_ATxmega256A3B__) \
539
|| defined(__AVR_ATxmega256A3BU__) \
540
|| defined(__AVR_ATxmega384C3__) \
541
|| defined(__AVR_ATxmega384D3__)
542
543
#define SLEEP_MODE_IDLE (0)
544
#define SLEEP_MODE_PWR_DOWN (SLEEP_SMODE1_bm)
545
#define SLEEP_MODE_PWR_SAVE (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
546
#define SLEEP_MODE_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
547
#define SLEEP_MODE_EXT_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
548
549
#define set_sleep_mode(mode) \
550
do { \
551
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
552
} while(0)
553
554
#elif defined(__AVR_AT90SCR100__) \
555
|| defined(__AVR_ATmega8U2__) \
556
|| defined(__AVR_ATmega16U2__) \
557
|| defined(__AVR_ATmega32U2__) \
558
|| defined(__AVR_AT90USB162__) \
559
|| defined(__AVR_AT90USB82__)
560
561
#define SLEEP_MODE_IDLE (0)
562
#define SLEEP_MODE_PWR_DOWN _BV(SM1)
563
#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
564
#define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
565
#define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
566
567
#define set_sleep_mode(mode) \
568
do { \
569
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
570
} while(0)
571
572
#elif defined(__AVR_ATA6285__) \
573
|| defined(__AVR_ATA6286__) \
574
|| defined(__AVR_ATA6289__)
575
576
#define SLEEP_MODE_IDLE (0)
577
#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (_BV(SM0))
578
#define SLEEP_MODE_PWR_DOWN (_BV(SM1))
579
580
#define set_sleep_mode(mode) \
581
do { \
582
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
583
} while(0)
584
585
#elif defined (__AVR_ATA5790__) \
586
|| defined (__AVR_ATA5790N__) \
587
|| defined (__AVR_ATA5795__) \
588
|| defined (__AVR_ATA5782__) \
589
|| defined (__AVR_ATA5831__)
590
591
#define SLEEP_MODE_IDLE (0)
592
#define SLEEP_MODE_EXT_PWR_SAVE (_BV(SM0))
593
#define SLEEP_MODE_PWR_DOWN (_BV(SM1))
594
#define SLEEP_MODE_PWR_SAVE (_BV(SM1) | _BV(SM0))
595
596
#define set_sleep_mode(mode) \
597
do { \
598
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
599
} while(0)
600
601
#elif defined (__AVR_ATA5702M322__)
602
603
#define SLEEP_MODE_IDLE (0)
604
#define SLEEP_MODE_EXT_PWR_SAVE (_BV(SM0))
605
#define SLEEP_MODE_PWR_DOWN (_BV(SM1))
606
#define SLEEP_MODE_PWR_SAVE (_BV(SM1) | _BV(SM0))
607
#define SLEEP_MODE_EXT_PWR_DOWN (_BV(SM2))
608
#define SLEEP_MODE_PWR_OFF (_BV(SM2) | _BV(SM0))
609
610
#define set_sleep_mode(mode) \
611
do { \
612
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
613
} while(0)
614
615
#elif defined(__AVR_ATtiny4__) \
616
|| defined(__AVR_ATtiny5__) \
617
|| defined(__AVR_ATtiny9__) \
618
|| defined(__AVR_ATtiny10__) \
619
|| defined(__AVR_ATtiny20__) \
620
|| defined(__AVR_ATtiny40__)
621
622
#define SLEEP_MODE_IDLE 0
623
#define SLEEP_MODE_ADC _BV(SM0)
624
#define SLEEP_MODE_PWR_DOWN _BV(SM1)
625
#define SLEEP_MODE_STANDBY _BV(SM2)
626
627
#define set_sleep_mode(mode) \
628
do { \
629
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
630
} while(0)
631
632
#else
633
634
#error "No SLEEP mode defined for this device."
635
636
#endif
637
638
639
640
/** \ingroup avr_sleep
641
642
Put the device in sleep mode. How the device is brought out of sleep mode
643
depends on the specific mode selected with the set_sleep_mode() function.
644
See the data sheet for your device for more details. */
645
646
647
#if defined(__DOXYGEN__)
648
649
/** \ingroup avr_sleep
650
651
Set the SE (sleep enable) bit.
652
*/
653
extern
void
sleep_enable
(
void
);
654
655
#else
656
657
#define sleep_enable() \
658
do { \
659
_SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK; \
660
} while(0)
661
662
#endif
663
664
665
#if defined(__DOXYGEN__)
666
667
/** \ingroup avr_sleep
668
669
Clear the SE (sleep enable) bit.
670
*/
671
extern
void
sleep_disable
(
void
);
672
673
#else
674
675
#define sleep_disable() \
676
do { \
677
_SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK); \
678
} while(0)
679
680
#endif
681
682
683
/** \ingroup avr_sleep
684
685
Put the device into sleep mode. The SE bit must be set
686
beforehand, and it is recommended to clear it afterwards.
687
*/
688
#if defined(__DOXYGEN__)
689
690
extern
void
sleep_cpu
(
void
);
691
692
#else
693
694
#define sleep_cpu() \
695
do { \
696
__asm__ __volatile__ ( "sleep" "\n\t" :: ); \
697
} while(0)
698
699
#endif
700
701
702
#if defined(__DOXYGEN__)
703
704
extern
void
sleep_mode (
void
);
705
706
#else
707
708
#define sleep_mode() \
709
do { \
710
sleep_enable(); \
711
sleep_cpu(); \
712
sleep_disable(); \
713
} while (0)
714
715
#endif
716
717
718
#if defined(__DOXYGEN__)
719
720
extern
void
sleep_bod_disable (
void
);
721
722
#else
723
724
#if defined(BODS) && defined(BODSE)
725
726
#ifdef BODCR
727
728
#define BOD_CONTROL_REG BODCR
729
730
#else
731
732
#define BOD_CONTROL_REG MCUCR
733
734
#endif
735
736
#define sleep_bod_disable() \
737
do { \
738
uint8_t tempreg; \
739
__asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \
740
"ori %[tempreg], %[bods_bodse]" "\n\t" \
741
"out %[mcucr], %[tempreg]" "\n\t" \
742
"andi %[tempreg], %[not_bodse]" "\n\t" \
743
"out %[mcucr], %[tempreg]" \
744
: [tempreg] "=&d" (tempreg) \
745
: [mcucr] "I" _SFR_IO_ADDR(BOD_CONTROL_REG), \
746
[bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \
747
[not_bodse] "i" (~_BV(BODSE))); \
748
} while (0)
749
750
#endif
751
752
#endif
753
754
755
/*@}*/
756
757
#endif
/* _AVR_SLEEP_H_ */
sleep_cpu
void sleep_cpu(void)
sleep_enable
void sleep_enable(void)
io.h
sleep_disable
void sleep_disable(void)
stdint.h
Automatically generated by Doxygen 1.8.8 on Thu Apr 2 2015.